/******************************************************************************
 * FILE:			ADT_L1.h
 *
 * Copyright (c) 2007-2016, Alta Data Technologies LLC (ADT), All Rights Reserved.
 * Use of this software is subject to the ADT Software License (latest
 * revision), US Government or local laws and the ADT Terms and Conditions
 * of Sale (latest revision).
 *
 * DESCRIPTION:
 *	Header file for Layer 1 API.
 *
 *****************************************************************************/
/*! \file ADT_L1.h
 *  \brief Top-level header file for the ADT Layer 1 API
 */
#ifndef _ADT_L1_Header_
#define _ADT_L1_Header_

#include "ADT_L0.h"

#ifdef __cplusplus
extern "C" {
#endif

/********** Constants **********/
/* L1 API Version Constant */
#define ADT_L1_API_VERSION	0x03010000  /* Version 3.1.0.0 */

/* Memory offsets (BYTE offsets) */
#define ADT_L1_MA4_START_A429_CHANNELS	0x00300000  /* Offset to first A429 channel on PMC-MA4 board (after Global Registers) - May Change in Future */

#define ADT_RW_MEM_MAX_SIZE 110 /* Max size for block read/write of 110 32-bit words (440 bytes) */

/* Sizes for memory management array */
#define ADT_L1_MEMMGT_NUM_BACKPLANE 3
#define ADT_L1_MEMMGT_NUM_BOARDTYPE 0x50
#define ADT_L1_MEMMGT_NUM_BOARDNUM  8		/* Max of 8 boards of a given type (was 16) */
#define ADT_L1_MEMMGT_NUM_CHANTYPE  49		/* 0 to 0x30 channel types (49) */
#define ADT_L1_MEMMGT_NUM_CHANNUM   16		/* Max of 16 channels of a given type */

/********** Global Device Registers **********/
/* ***  See AltaCore-1553 Manual: Global Card Level Registers *** */
#define ADT_L1_GLOBAL_PRODIDREV		0x0040
#define		ADT_L1_GLOBAL_PRODIDREV_ENET1553	0x600E
#define		ADT_L1_GLOBAL_PRODIDREV_PMCE1553	0x6018
#define		ADT_L1_GLOBAL_PRODIDREV_ENETA429	0x6019
#define		ADT_L1_GLOBAL_PRODIDREV_ENET1A1553	0x601A
#define		ADT_L1_GLOBAL_PRODIDREV_ENET485		0x601E
#define		ADT_L1_GLOBAL_PRODIDREV_ENET2_1553	0x601F
#define		ADT_L1_GLOBAL_PRODIDREV_ENET_MA4	0x6024
#define		ADT_L1_GLOBAL_PRODIDREV_ENETX_MA4	0x6028
#define		ADT_L1_GLOBAL_PRODIDREV_ENETA429P	0x602A
#define ADT_L1_GLOBAL_CAPREG		0x0044
#define		ADT_L1_GLOBAL_CAPREG_1553CHEN		0x000000FF
#define		ADT_L1_GLOBAL_CAPREG_FLSHREAD		0x00000100
#define		ADT_L1_GLOBAL_CAPREG_1553VV			0x00000200
#define		ADT_L1_GLOBAL_CAPREG_1553FF			0x00000400
#define		ADT_L1_GLOBAL_CAPREG_IRIG			0x00000800
#define		ADT_L1_GLOBAL_CAPREG_1553ALTARTVAL	0x00004000
#define		ADT_L1_GLOBAL_CAPREG_ALTAVIEW		0x00008000
#define		ADT_L1_GLOBAL_CAPREG_ARINCBNK1EN	0x01000000
#define		ADT_L1_GLOBAL_CAPREG_ARINCBNK2EN	0x02000000
#define ADT_L1_GLOBAL_SERNUM		0x0048
#define ADT_L1_GLOBAL_ALIGNCHECK	0x004C
#define ADT_L1_GLOBAL_MEMSIZE		0x0050
#define ADT_L1_GLOBAL_CSR			0x0054
#define		ADT_L1_GLOBAL_CSR_CLRTT				0x00000001
#define		ADT_L1_GLOBAL_CSR_SETTT				0x00000002
#define		ADT_L1_GLOBAL_CSR_IRIG_LATCH		0x00000004
#define		ADT_L1_GLOBAL_CSR_IRIG_DETECT		0x00000008
#define		ADT_L1_GLOBAL_CSR_IRIG_LOCK			0x00000010
#define		ADT_L1_GLOBAL_CSR_FRCTRG			0x00000020
#define		ADT_L1_GLOBAL_CSR_EC_SRCIN_485		0x00001000
#define		ADT_L1_GLOBAL_CSR_EC_SRCIN_TTL		0x00002000
#define		ADT_L1_GLOBAL_CSR_EC_SRCOUT_485		0x00010000
#define		ADT_L1_GLOBAL_CSR_EC_SRCOUT_TTL		0x00020000
#define		ADT_L1_GLOBAL_CSR_EC_FRQOUT_1MHZ	0x00040000
#define		ADT_L1_GLOBAL_CSR_EC_FRQOUT_5MHZ	0x00080000
#define		ADT_L1_GLOBAL_CSR_EC_FRQOUT_10MHZ	0x00100000
#define		ADT_L1_GLOBAL_CSR_LED1ON			0x40000000
#define		ADT_L1_GLOBAL_CSR_LED2ON			0x80000000
#define ADT_L1_GLOBAL_INTPENDING	0x0058
#define		ADT_L1_GLOBAL_INTPENDING_CH1PEND	0x00000001
#define		ADT_L1_GLOBAL_INTPENDING_CH2PEND	0x00000002
#define		ADT_L1_GLOBAL_INTPENDING_CH3PEND	0x00000004
#define		ADT_L1_GLOBAL_INTPENDING_CH4PEND	0x00000008
#define		ADT_L1_GLOBAL_INTPENDING_CH1LTCH	0x00010000
#define		ADT_L1_GLOBAL_INTPENDING_CH2LTCH	0x00020000
#define		ADT_L1_GLOBAL_INTPENDING_CH3LTCH	0x00040000
#define		ADT_L1_GLOBAL_INTPENDING_CH4LTCH	0x00080000
#define		ADT_L1_GLOBAL_INTPENDING_LTCHHWINT	0x80000000
#define ADT_L1_GLOBAL_TRIGGERCSR	0x005C
#define ADT_L1_GLOBAL_SGLEDISCSTS	0x0080
#define ADT_L1_GLOBAL_SGLEDISCCTL	0x0084
#define ADT_L1_GLOBAL_DIFFDISCSTS	0x00A0
#define ADT_L1_GLOBAL_DIFFDISCCTL	0x00A4
#define ADT_L1_GLOBAL_I2CCTL		0x00C0
#define ADT_L1_GLOBAL_I2CSTS		0x00C4
#define		ADT_L1_GLOBAL_I2C_TS_FPGA_ADDR	0x00000090
#define		ADT_L1_GLOBAL_I2C_TS_XCVR_ADDR	0x00000092
#define ADT_L1_GLOBAL_IRIGTIME_HIGH 0x00C8
#define ADT_L1_GLOBAL_IRIGTIME_LOW  0x00CC

/********** Common Device Registers **********/
/* *** AltaCore-1553 Manual: Root PE Channel Registers *** */
/* All Alta devices will have these registers in the same locations */
#define ADT_L1_PE_ROOT_IDVER		0x0008
#define ADT_L1_PE_BITSTATUS			0x002C
#define ADT_L1_PE_INUSE				0x0030

/********** Common Device Startup Options *********/
/* *** AltaAPI Manual: See ADT_L1_XXXX_InitDefault_ExtendedOptions() *** */
/* DEVICE API Only Definitions */
#define	ADT_L1_API_DEVICEINIT_FORCEINIT				0x00000001
#define	ADT_L1_API_DEVICEINIT_NOMEMTEST				0x00000002
#define	ADT_L1_API_DEVICEINIT_NOKP					ADT_L0_API_DEVICEINIT_NOKP
#define	ADT_L1_API_DEVICEINIT_ROOTPERESET			0x80000000

/*******************************************/
/********** 1553 Device Registers **********/
#define ADT_L1_1553_CHAN_REGS		0x0000

/* 1553 Root PE Registers */
/* *** AltaCore-1553 Manual: Root PE Channel Registers *** */
#define ADT_L1_1553_PE_ROOT_CSR		0x0000
#define		ADT_L1_1553_PECSR_HWINTON			0x00000001
#define		ADT_L1_1553_PECSR_BCAST				0x00000002
#define		ADT_L1_1553_PECSR_INTBUS			0x00000004
#define		ADT_L1_1553_PECSR_MRT				0x00000008
#define		ADT_L1_1553_PECSR_SGON				0x00000010
#define		ADT_L1_1553_PECSR_CLKTRGON			0x00000020
#define		ADT_L1_1553_PECSR_FRCTRGIN			0x00000040
#define		ADT_L1_1553_PECSR_FRCTRGOUT			0x00000080
#define		ADT_L1_1553_PECSR_RDIRIGTM			0x00000100
#define		ADT_L1_1553_PECSR_ZEROTT			0x00000200
#define		ADT_L1_1553_PECSR_SETTT				0x00000400
#define		ADT_L1_1553_PECSR_READTT			0x00000800
#define		ADT_L1_1553_PECSR_USE_EC			0x00001000
#define		ADT_L1_1553_PECSR_EC_FRQIN_1MHZ		0x00002000
#define		ADT_L1_1553_PECSR_EC_FRQIN_5MHZ		0x00004000
#define		ADT_L1_1553_PECSR_EC_FRQIN_10MHZ	0x00008000
#define		ADT_L1_1553_PECSR_RS485_TRIG_IN  	0x00010000
#define		ADT_L1_1553_PECSR_RS485_TRIG_OUT	0x00020000
#define		ADT_L1_1553_PECSR_RS485_LINKSPEC	0x00040000
#define     ADT_L1_1553_PECSR_SDISC_TRIG_IN		0x00080000
#define		ADT_L1_1553_PECSR_PB_SETTT			0x00100000
#define		ADT_L1_1553_PECSR_PB_READTT			0x00200000
#define		ADT_L1_1553_PECSR_TRIGINLOWTOHIGH	0x00400000
#define		ADT_L1_1553_PECSR_GENTRGONEVNTGAP	0x00800000
#define		ADT_L1_1553_PECSR_BUS_B_ONLY		0x04000000
#define		ADT_L1_1553_PECSR_BUS_A_ONLY		0x08000000
#define		ADT_L1_1553_PECSR_BITFAIL_INT		0x20000000
#define		ADT_L1_1553_PECSR_RUNIBIT			0x40000000
#define		ADT_L1_1553_PECSR_CHAN_RESET		0x80000000

#define ADT_L1_1553_PE_ROOT_STS		0x0004
#define		ADT_L1_1553_PESTS_INTPND	0x00000001
#define ADT_L1_1553_PE_ROOT_IDVER	ADT_L1_PE_ROOT_IDVER
#define ADT_L1_1553_PE_MONCMDCNTR	0x000C
#define ADT_L1_1553_PE_MONERRCNTR	0x0010
#define ADT_L1_1553_PE_BCBM_TIMEOUT	0x0014
#define ADT_L1_1553_PE_RTMODE		0x0018
#define ADT_L1_1553_PE_TIMEHIGH		0x001C
#define ADT_L1_1553_PE_TIMELOW		0x0020
#define ADT_L1_1553_PE_IRIGTIMEHIGH	0x0024
#define ADT_L1_1553_PE_IRIGTIMELOW	0x0028
#define ADT_L1_1553_PE_BITSTATUS	ADT_L1_PE_BITSTATUS
#define		ADT_L1_1553_BIT_ENCDECFAIL	0x00000001
#define		ADT_L1_1553_BIT_MEMTESTFAIL	0x00000002
#define		ADT_L1_1553_BIT_PROCFAIL	0x00000004
#define		ADT_L1_1553_BIT_TTAGFAIL	0x00000008
#define		ADT_L1_1553_BIT_TIMEOUTFAIL	0x00000010
#define		ADT_L1_1553_BIT_LOOPFAIL	0x00000020
#define		ADT_L1_1553_BIT_POSTFAIL	0x01000000
#define		ADT_L1_1553_BIT_PBITFAIL	0x02000000
#define		ADT_L1_1553_BIT_IBITFAIL	0x04000000
#define		ADT_L1_1553_BIT_POSTINPROG	0x10000000
#define		ADT_L1_1553_BIT_PBITINPROG	0x20000000
#define		ADT_L1_1553_BIT_IBITINPROG	0x40000000
#define ADT_L1_1553_PE_INUSE		ADT_L1_PE_INUSE
#define ADT_L1_1553_PE_SC_CSR_BUSA	0x0034
#define ADT_L1_1553_PE_SC_CSR_MASKA	0x0038
#define ADT_L1_1553_PE_SC_DATA_BUSA 0x003C
#define ADT_L1_1553_PE_SC_CSR_BUSB	0x0040
#define ADT_L1_1553_PE_SC_CSR_MASKB	0x0044
#define ADT_L1_1553_PE_SC_DATA_BUSB 0x0048
#define		ADT_L1_1553_PE_SC_CSR_DATARDY			0x80000000
#define		ADT_L1_1553_PE_SC_CSR_FIFONOTEMPTY		0x40000000
#define		ADT_L1_1553_PE_SC_CSR_TIMEDELAY			0x01FF0000
#define		ADT_L1_1553_PE_SC_CSR_TRG_MASK_ERROR	0x00000020
#define		ADT_L1_1553_PE_SC_CSR_TRG_STATUS_MASK	0x00000010
#define		ADT_L1_1553_PE_SC_CSR_TRG_DATA_MASK		0x00000008
#define		ADT_L1_1553_PE_SC_CSR_TRG_CMD_MASK		0x00000004
#define		ADT_L1_1553_PE_SC_CSR_TRG_ERROR			0x00000002
#define		ADT_L1_1553_PE_SC_CSR_TRG_ANYACT		0x00000001
#define ADT_L1_1553_PE_INTVLTMR		0x004C
#define		ADT_L1_1553_PE_INTVLTMR_STARTSTOP	0x00000001
#define		ADT_L1_1553_PE_INTVLTMR_STARTONTRIG	0x00000002
#define		ADT_L1_1553_PE_INTVLTMR_READTIMER	0x00000004
#define		ADT_L1_1553_PE_INTVLTMR_EXTTRIG		0x00000008
#define		ADT_L1_1553_PE_INTVLTMR_SETINT		0x00000010
#define		ADT_L1_1553_PE_INTVLTMR_USEEXTCLK	0x00000020
#define     ADT_L1_1553_PE_INTVLTMR_AUTOREARM   0x00000040
#define		ADT_L1_1553_PE_INTVLTMR_TIMECOMP	0x00000080
#define		ADT_L1_1553_PE_INTVLTMR_TIME24		0xFFFFFF00
#define		ADT_L1_1553_PE_INTVLTMR_TIMESHIFT	8
#define ADT_L1_EBR1553_PE_RTINHIBIT 0x0050
#define ADT_L1_1553_PE_INTPENDING	0x00E0

/* 1553 Root BC Registers */
/* *** AltaCore-1553 Manual: Bus Controller (BC) *** */
#define ADT_L1_1553_BC_FIRSTBCCB	0x0100
#define ADT_L1_1553_BC_CURRBCCB		0x0104
#define		ADT_L1_1553_BC_NO_NEXT_MSG			0xFFFFFFFF
#define ADT_L1_1553_BC_CSR			0x0108
#define		ADT_L1_1553_BC_CSR_RUN				0x00000001
#define		ADT_L1_1553_BC_CSR_STOPPED			0x00000002
#define		ADT_L1_1553_BC_CSR_FRMOFLOW			0x00000010
#define		ADT_L1_1553_BC_CSR_STOPONOFLOW		0x00000020
#define		ADT_L1_1553_BC_CSR_EN_SUBFRAMES		0x00000040
#define		ADT_L1_1553_BC_CSR_INTONFRMOFLOW	0x00002000
#define		ADT_L1_1553_BC_CSR_INTONSTOP		0x00004000
#define		ADT_L1_1553_BC_CSR_INTONRETRYCMPLT	0x00008000
#define ADT_L1_1553_BC_RESERVED		0x010C
#define ADT_L1_1553_BC_MINPERMAJ	0x0110
#define ADT_L1_1553_BC_MINORFRMCNT	0x0114
#define ADT_L1_1553_BC_MAXFRAMECNT  0x0118
#define ADT_L1_1553_BC_TOTALFRMCNT	0x011C
#define ADT_L1_1553_BC_HPAMPTR		0x0120
#define ADT_L1_1553_BC_LPAMPTR		0x0124
#define ADT_L1_1553_BC_LPAMTIME		0x0128
#define ADT_L1_1553_BC_APIBCCBPTR	0x0178
#define ADT_L1_1553_BC_APIBCCBSIZE	0x017C

/* 1553 Root RT Registers */
/* *** AltaCore-1553 Manual: Remote Terminal (RT) *** */
#define ADT_L1_1553_RT_CSR			0x0180
#define		ADT_L1_1553_CSR_RT_ALLON			0x00000001
#define		ADT_L1_1553_CSR_RT_ALWTXINH			0x00000002
#define		ADT_L1_1553_CSR_RT_DONTINCCDP		0x00000004
#define     ADT_L1_1553_CSR_RT_MC01TTRESET      0x00001000
#define     ADT_L1_1553_CSR_RT_MC01TRIGOUT      0x00002000
#define		ADT_L1_1553_CSR_RT_EXTRTPERR		0x80000000
#define ADT_L1_1553_RT_CTLBLOCKS	0x0400

/* 1553 Root Bus Monitor (BM) Sequential Monitor Registers */
/* *** AltaCore-1553 Manual: Sequential Monitor (SM) *** */
#define ADT_L1_1553_BM_STARTCDP		0x01C0
#define ADT_L1_1553_BM_CURRENTCDP	0x01C4
#define ADT_L1_1553_BM_CSR			0x01C8
#define		ADT_L1_1553_BM_CSR_ON				0x00000001
#define		ADT_L1_1553_BM_CSR_MSGTRGON			0x00000002
#define		ADT_L1_1553_BM_CSR_WAITEXTTRG		0x00000004
#define		ADT_L1_1553_BM_CSR_STORESPURDATA	0x00000008
#define		ADT_L1_1553_BM_CSR_INTVLTMRRSVD3	0x00000010
#define		ADT_L1_1553_BM_CSR_ENET_APMP_ENABLE	0x00000100
#define		ADT_L1_1553_BM_CSR_ENET_APMP_PEIRIG	0x00000200
#define		ADT_L1_1553_BM_CSR_ENET_APMP_PEINTV	0x00000400
#define ADT_L1_1553_BM_CDPCOUNT		0x01CC
#define ADT_L1_1553_BM_RESV_API_END 0x01F8
#define ADT_L1_1553_BM_RESV_API		0x01FC
#define ADT_L1_1553_BM_FILTERS		0x0600

/* 1553 Root Interrupt Registers */
/* *** AltaCore-1553 Manual: Interrupt Functions *** */
#define ADT_L1_1553_IQ_START_IQP	0x0200
#define ADT_L1_1553_IQ_CURR_IQP		0x0204
#define ADT_L1_1553_IQ_SEQNUM		0x0208
#define ADT_L1_1553_IQ_RESV_API		0x023C

/* 1553 Root Signal Generator (SG) Registers */
/* *** AltaCore-1553 Manual: Signal Generator (SG) *** */
#define ADT_L1_1553_SG_STARTSGCB	0x0240
#define ADT_L1_1553_SG_CURRSGCB		0x0244
#define ADT_L1_1553_SG_USERCOUNT	0x0248
#define ADT_L1_1553_SG_PECOUNT		0x024C
#define ADT_L1_1553_SG_PEOFFSET		0x0250

/* 1553 Root Playback Registers */
/* *** AltaCore-1553 Manual: Playback (PB) *** */
#define ADT_L1_1553_PB_STARTPBPTR	0x0280
#define ADT_L1_1553_PB_CURRPBPTR	0x0284
#define ADT_L1_1553_PB_CSR			0x0288
#define		ADT_L1_1553_PB_CSR_PBRUN		0x00000001
#define		ADT_L1_1553_PB_CSR_TRGIN		0x00000002
#define		ADT_L1_1553_PB_CSR_NOCLKRST		0x00000010
#define		ADT_L1_1553_PB_CSR_SKPPCBTMBKUP	0x00000020
#define ADT_L1_1553_PB_CURROFFSET	0x028C
#define ADT_L1_1553_PB_API1STTIMEHI 0x02B0
#define ADT_L1_1553_PB_API1STTIMELO 0x02B4
#define ADT_L1_1553_PB_APIRTRESPWD	0x02B8
#define ADT_L1_1553_PB_APITAILPTR	0x02BC

/********* 1553 Extended Memory Data Structures *********/
/* 1553 RT Control Block Offsets (BYTE offsets) */
/* *** AltaCore-1553 Manual: Remote Terminal (RT) *** */
#define   ADT_L1_1553_RT_CB_FTPTR			0x0000
#define   ADT_L1_1553_RT_CB_RTCSR			0x0004
#define		ADT_L1_1553_CSR_RT_ON				0x00000001
#define		ADT_L1_1553_CSR_RT_STSMON			0x00000002
#define		ADT_L1_1553_CSR_RT_CLRSRTXMC		0x00000010
#define		ADT_L1_1553_CSR_RT_PEINHTMFG		0x00000040
#define		ADT_L1_1553_CSR_RT_PETXIHBTA		0x00000080
#define		ADT_L1_1553_CSR_RT_PETXIHBTB		0x00000100
#define		ADT_L1_1553_CSR_RT_ALLOWDBC			0x00000200
#define		ADT_L1_1553_CSR_RT_PEFORCEIHBTA		0x00000400
#define		ADT_L1_1553_CSR_RT_PEFORCEIHBTB		0x00000800
#define		ADT_L1_1553_CSR_RT_INJSTSPARERR		0x10000000
#define		ADT_L1_1553_CSR_RT_INJSTSMANERR		0x20000000
#define		ADT_L1_1553_CSR_RT_INJSTSSYNCERR	0x40000000
#define   ADT_L1_1553_RT_CB_RTSTS			0x0008
#define   ADT_L1_1553_RT_CB_RTLCMD			0x000C
#define			ADT_L1_1553_RT_SA_CB_CDPPTR			0x0000
#define			ADT_L1_1553_RT_SA_CB_ILLEGALBITS	0x0004
#define			ADT_L1_1553_RT_SA_CB_APINUMCDP		0x0008
#define			ADT_L1_1553_RT_SA_CB_APISTARTCDP	0x000C
#define     ADT_L1_1553_RT_FT_RXSA				0x0000
#define     ADT_L1_1553_RT_FT_TXSA				0x0080
#define     ADT_L1_1553_RT_FT_RXMC				0x0100
#define		ADT_L1_1553_RT_FT_TXMC				0x0180

/* 1553 BC Control Block Offsets (BYTE offsets) */
/* *** AltaCore-1553 Manual: Bus Controller (BC) *** */
#define ADT_L1_1553_BC_CB_NEXTPTR	0x0000
#define ADT_L1_1553_BC_CB_CDPPTR	0x0004
#define ADT_L1_1553_BC_CB_RETRY		0x0008
#define		ADT_L1_1553_BC_CB_RETRY_ENABLEONERR	0x00000001
#define		ADT_L1_1553_BC_CB_RETRY_ENABLEONBSY	0x00000002
#define		ADT_L1_1553_BC_CB_RETRY_NUMATTEMPTD	0x000000F0
#define		ADT_L1_1553_BC_CB_RETRY_CURPENUM	0x00000F00
#define		ADT_L1_1553_BC_CB_RETRY_MAXNUMSET	0x0000F000
#define		ADT_L1_1553_BC_CB_RETRY_BUSPATTERN	0xFFFF0000
#define ADT_L1_1553_BC_CB_CSR		0x000C
#define		ADT_L1_1553_BC_CB_CSR_HALTONERROR	0x00000001
#define		ADT_L1_1553_BC_CB_CSR_BUSA			0x00000002
#define		ADT_L1_1553_BC_CB_CSR_BUSB			0x00000000
#define		ADT_L1_1553_BC_CB_CSR_STARTFRAME	0x00000004
#define		ADT_L1_1553_BC_CB_CSR_ENDFRAME		0x00000008
#define		ADT_L1_1553_BC_CB_CSR_SCHEDTIMING	0x00000010
#define		ADT_L1_1553_BC_CB_CSR_WAITFORTRG	0x00000020
#define		ADT_L1_1553_BC_CB_CSR_GENEXTTRG		0x00000040
#define		ADT_L1_1553_BC_CB_CSR_INTMSGCOMP	0x00000100
#define		ADT_L1_1553_BC_CB_CSR_BCRTTIMEWRDS	0x00008000
#define		ADT_L1_1553_BC_CB_CSR_ADDRBRANCH	0x00100000
#define		ADT_L1_1553_BC_CB_CSR_CDPBRANCHONLY 0x00200000
#define		ADT_L1_1553_BC_CB_CSR_DELAYONLY	    0x00400000
#define		ADT_L1_1553_BC_CB_CSR_BRNCHONVALUE	0x00800000
#define		ADT_L1_1553_BC_CB_CSR_BRNCHRETURN	0x01000000
#define		ADT_L1_1553_BC_CB_CSR_TYPE_NOP		0x02000000
#define		ADT_L1_1553_BC_CB_CSR_TYPE_BCRT		0x04000000
#define		ADT_L1_1553_BC_CB_CSR_TYPE_RTBC		0x08000000
#define		ADT_L1_1553_BC_CB_CSR_TYPE_RTRT		0x10000000
#define		ADT_L1_1553_BC_CB_CSR_TYPE_MCDATA	0x20000000
#define		ADT_L1_1553_BC_CB_CSR_TYPE_MCNODATA	0x40000000
#define ADT_L1_1553_BC_CB_CMD1INFO	0x0010
#define ADT_L1_1553_BC_CB_CMD2INFO	0x0014
#define		ADT_L1_1553_CMD_WRDINFO_1553BITS	0x0000FFFF
#define		ADT_L1_1553_CMD_WRDINFO_GAPTIME		0x00FF0000
#define		ADT_L1_1553_CMD_WRDINFO_TXGAP		0x02000000
#define		ADT_L1_1553_CMD_WRDINFO_TXPARERR	0x10000000
#define		ADT_L1_1553_CMD_WRDINFO_TXMANERR	0x20000000
#define		ADT_L1_1553_CMD_WRDINFO_TXSYNCERR	0x40000000
#define ADT_L1_1553_BC_CB_FRAMETIME	0x0018
#define ADT_L1_1553_BC_CB_DELAYTIME	0x001C
#define ADT_L1_1553_BC_CB_BRANCHADD	0x0020
#define ADT_L1_1553_BC_CB_STARTFRM	0x0024
#define ADT_L1_1553_BC_CB_STOPFRM	0x0028
#define ADT_L1_1553_BC_CB_REPRATE	0x002C
#define ADT_L1_1553_BC_CB_NXTXMIT	0x0030
#define ADT_L1_1553_BC_CB_APIMSGNUM	0x0034
#define ADT_L1_1553_BC_CB_APINUMCDP 0x0038
#define ADT_L1_1553_BC_CB_API1STCDP 0x003C

/* 1553 SG Control Block Offsets (BYTE offsets) */
/* *** AltaCore-1553 Manual: Signal Generator (SG) *** */
#define ADT_L1_1553_SGCB_NEXTPTR	0x0000
#define ADT_L1_1553_SGCB_CSR		0x0004
#define ADT_L1_1553_SGCB_TIMEHIGH	0x0008
#define ADT_L1_1553_SGCB_TIMELOW	0x000C
#define ADT_L1_1553_SGCB_VECCOUNT	0x0010
#define ADT_L1_1553_SGCB_VECTORS	0x0014

/* 1553 SG Vector Constants */
/* *** AltaCore-1553 Manual: Signal Generator (SG) *** */
#define ADT_L1_1553_SG_VECTOR_GND0	0
#define ADT_L1_1553_SG_VECTOR_LOW	1
#define ADT_L1_1553_SG_VECTOR_HIGH	2
#define ADT_L1_1553_SG_VECTOR_GND1	3

/* 1553 CDP Offsets (BYTE offsets) */
/* *** AltaCore-1553 Manual: Common Data Packet (CDP) *** */
#define	ADT_L1_1553_CDP_BYTECNT		196
#define	ADT_L1_1553_CDP_WRDCNT		49
#define ADT_L1_1553_CDP_NEXT		0x0000
#define ADT_L1_1553_CDP_BMCOUNT		0x0004
#define	ADT_L1_1553_CDP_RESV_API	0x0008
#define		ADT_L1_1553_CDP_RAPI_RT_ID			0x80000000
#define		ADT_L1_1553_CDP_RAPI_MC_ID			0x40000000
#define		ADT_L1_1553_CDP_RAPI_RT_RTADDR		20
#define		ADT_L1_1553_CDP_RAPI_RT_TR			18
#define		ADT_L1_1553_CDP_RAPI_RT_SA			12
#define		ADT_L1_1553_CDP_RAPI_RT_BUFNUM		0
#define		ADT_L1_1553_CDP_RAPI_BC_ID			0x20000000
#define		ADT_L1_1553_CDP_RAPI_BC_MSGNUM		12
#define		ADT_L1_1553_CDP_RAPI_BC_BUFNUM		0
#define		ADT_L1_1553_CDP_RAPI_BM_ID			0x10000000
#define		ADT_L1_1553_CDP_RAPI_BM_BUFNUM		0
#define ADT_L1_1553_CDP_RSVD1		0x000C
#define ADT_L1_1553_CDP_RSVD2		0x0010
#define ADT_L1_1553_CDP_MASKVALUE	0x0014
#define ADT_L1_1553_CDP_MASKCOMPARE	0x0018
#define ADT_L1_1553_CDP_CONTROL		0x001C
#define		ADT_L1_1553_CDP_CONTROL_TXERRINJ	0x00000002
#define		ADT_L1_1553_CDP_CONTROL_INTERR		0x00000010
#define		ADT_L1_1553_CDP_CONTROL_INTNOERR	0x00000020
#define		ADT_L1_1553_CDP_CONTROL_INTCMPTRUE	0x00000040
#define		ADT_L1_1553_CDP_CONTROL_LEDONCMPLT	0x00000400
#define		ADT_L1_1553_CDP_CONTROL_TRGOUTERR	0x00002000
#define		ADT_L1_1553_CDP_CONTROL_TRGOUTNOERR	0x00004000
#define		ADT_L1_1553_CDP_CONTROL_TRGOUTCMPTR	0x00008000
#define		ADT_L1_1553_CDP_CONTROL_CDPCMP		16
#define		ADT_L1_1553_CDP_CONTROL_FRCDWCNUM	24
#define		ADT_L1_1553_CDP_CONTROL_FRCDWCON	0x40000000
#define ADT_L1_1553_CDP_STATUS		0x0020
#define		ADT_L1_1553_CDP_STATUS_MSGWC		0x0000003F
#define		ADT_L1_1553_CDP_STATUS_BUSAB		0x00000040
#define		ADT_L1_1553_CDP_STATUS_TWOBUSERR	0x00000100
#define		ADT_L1_1553_CDP_STATUS_STSWRNGADD	0x00000200
#define		ADT_L1_1553_CDP_STATUS_NORESP		0x00000400
#define		ADT_L1_1553_CDP_STATUS_WCERR		0x00000800
#define		ADT_L1_1553_CDP_STATUS_PARERR		0x00001000
#define		ADT_L1_1553_CDP_STATUS_BITERR		0x00002000
#define		ADT_L1_1553_CDP_STATUS_SYNCERR		0x00004000
#define		ADT_L1_1553_CDP_STATUS_NOERR		0x00008000
#define		ADT_L1_1553_CDP_STATUS_CMPTRUE		0x00010000
#define		ADT_L1_1553_CDP_STATUS_SPURMSG		0x04000000
#define		ADT_L1_1553_CDP_STATUS_BCRTMSG		0x08000000
#define		ADT_L1_1553_CDP_STATUS_RTBCMSG		0x10000000
#define		ADT_L1_1553_CDP_STATUS_RTRTMSG		0x20000000
#define		ADT_L1_1553_CDP_STATUS_MCMSG		0x40000000
#define		ADT_L1_1553_CDP_STATUS_BRDCSTMSG	0x80000000
#define ADT_L1_1553_CDP_TIMEHIGH	0x0024
#define ADT_L1_1553_CDP_TIMELOW		0x0028
#define ADT_L1_1553_CDP_IMGAP		0x002C
#define ADT_L1_1553_CDP_RSVD3		0x0030
#define ADT_L1_1553_CDP_CMD1INFO	0x0034
#define ADT_L1_1553_CDP_CMD2INFO	0x0038
#define ADT_L1_1553_CDP_STS1INFO	0x003C
#define ADT_L1_1553_CDP_STS2INFO	0x0040
#define ADT_L1_1553_CDP_DATA1INFO	0x0044
#define		ADT_L1_1553_CDP_WRDINFO_1553BITS	0x0000FFFF
#define		ADT_L1_1553_CDP_WRDINFO_GAPTIME		0x00FF0000
#define		ADT_L1_1553_CDP_WRDINFO_GAPTIMEOSET	16
#define		ADT_L1_1553_CDP_WRDINFO_RXADDTXGAP	0x02000000
#define		ADT_L1_1553_CDP_WRDINFO_RXNORESP	0x04000000
#define		ADT_L1_1553_CDP_WRDINFO_RXWCERR		0x08000000
#define		ADT_L1_1553_CDP_WRDINFO_RXTXPARERR	0x10000000
#define		ADT_L1_1553_CDP_WRDINFO_RXTXMANERR	0x20000000
#define		ADT_L1_1553_CDP_WRDINFO_RXTXSYNCERR	0x40000000
#define		ADT_L1_1553_CDP_WRDINFO_RXBUSAB		0x80000000

/* 1553 Playback Packet Offsets (BYTE offsets) */
/* *** AltaCore-1553 Manual: Playback (PB) *** */
#define ADT_L1_1553_PBP_NEXTPTR		0x0000
#define ADT_L1_1553_PBP_CURROFFSET	0x0004
#define ADT_L1_1553_PBP_CONTROL		0x0008
#define		ADT_L1_1553_PBP_CONTROL_WDCNT	0x0000003F
#define		ADT_L1_1553_PBP_CONTROL_INT		0x00000040
#define		ADT_L1_1553_PBP_CONTROL_TRGOUT	0x00000080
#define		ADT_L1_1553_PBP_CONTROL_LED		0x00000100
#define		ADT_L1_1553_PBP_CONTROL_STOP	0x00000200
#define ADT_L1_1553_PBP_TIME_HIGH	0x000C
#define ADT_L1_1553_PBP_TIME_LOW	0x0010
#define ADT_L1_1553_PBP_DATASTART	0x0020
#define		ADT_L1_1553_PBP_DATA_WORD		0x0000FFFF
#define		ADT_L1_1553_PBP_DATA_GAP		0x00FF0000
#define		ADT_L1_1553_PBP_DATA_GAPOFFSET	16
#define		ADT_L1_1553_PBP_DATA_CMDSYNC	0x01000000
#define		ADT_L1_1553_PBP_DATA_ERRPARITY	0x10000000
#define		ADT_L1_1553_PBP_DATA_ERRMANCH	0x20000000
#define		ADT_L1_1553_PBP_DATA_ERRSYNC	0x40000000
#define		ADT_L1_1553_PBP_DATA_BUSA		0x80000000

/* 1553 Playback: API Option Bit for ADT_L1_1553_PB_CDPWrite() */
#define		ADT_L1_1553_API_PB_CDPWRITE_ATON	0x80000000

/* 1553 Interrupt Offsets (BYTE offsets) */
/* *** AltaCore-1553 Manual: Interrupt Functions *** */
#define	ADT_L1_1553_IQP_NEXTPTR 0x0000
#define	ADT_L1_1553_IQP_TYPESEQ 0x0004
#define		ADT_L1_1553_IQP_TYPESEQ_SEQNUM	0x0000FFFF
#define		ADT_L1_1553_IQP_TYPESEQ_SG		0x00010000
#define		ADT_L1_1553_IQP_TYPESEQ_PB		0x00020000
#define		ADT_L1_1553_IQP_TYPESEQ_BIT		0x00100000
#define		ADT_L1_1553_IQP_TYPESEQ_INTVLTMR 0x00200000
#define		ADT_L1_1553_IQP_TYPESEQ_BCCB	0x02000000
#define		ADT_L1_1553_IQP_TYPESEQ_BCFRMOVR 0x04000000
#define		ADT_L1_1553_IQP_TYPESEQ_BCSTOP	0x08000000
#define		ADT_L1_1553_IQP_TYPESEQ_BCRETRY	0x10000000
#define		ADT_L1_1553_IQP_TYPESEQ_BCCDP	0x20000000
#define		ADT_L1_1553_IQP_TYPESEQ_RTCDP	0x40000000
#define		ADT_L1_1553_IQP_TYPESEQ_BMCDP	0x80000000
#define	ADT_L1_1553_IQP_DSPTR	0x0008


/*******************************************/
/********** A429 Device Registers **********/
#define ADT_L1_A429_CHAN_REGS			0x0000

/* A429 Root PE Registers */
/* *** AltaCore-ARINC: Root PE Device/Bank Registers *** */
#define ADT_L1_A429_PE_ROOT_CSR			0x0000	/* A429 ROOT PE CONTROL REG */
#define		ADT_L1_A429_PECSR_HWINTON			0x00000001
#define		ADT_L1_A429_PECSR_SGON				0x00000010
#define		ADT_L1_A429_PECSR_CLKTRGON			0x00000020
#define		ADT_L1_A429_PECSR_FRCTRGIN			0x00000040
#define		ADT_L1_A429_PECSR_FRCTRGOUT			0x00000080
#define		ADT_L1_A429_PECSR_RDIRIGTM			0x00000100
#define		ADT_L1_A429_PECSR_ZEROTT			0x00000200
#define		ADT_L1_A429_PECSR_SETTT				0x00000400
#define		ADT_L1_A429_PECSR_READTT			0x00000800
#define		ADT_L1_A429_PECSR_USE_EC			0x00001000
#define		ADT_L1_A429_PECSR_EC_FRQIN_1MHZ		0x00002000
#define		ADT_L1_A429_PECSR_EC_FRQIN_5MHZ		0x00004000
#define		ADT_L1_A429_PECSR_EC_FRQIN_10MHZ	0x00008000
#define		ADT_L1_A429_PECSR_SGCHNUM			16
#define		ADT_L1_A429_PECSR_PB_SETTT			0x00100000
#define		ADT_L1_A429_PECSR_PB_READTT			0x00200000
#define		ADT_L1_A429_PECSR_TRIGINLOWTOHIGH	0x00400000
#define		ADT_L1_A429_PECSR_PBON				0x00800000
#define		ADT_L1_A429_PECSR_NOCLKRST			0x01000000
#define		ADT_L1_A429_PECSR_SKPPCBTMBKUP		0x02000000
#define		ADT_L1_A429_PECSR_ENET_APMP_ENABLE	0x04000000
#define		ADT_L1_A429_PECSR_ENET_APMP_PEIRIG	0x08000000
#define		ADT_L1_A429_PECSR_ENET_APMP_PEINTV	0x10000000
#define		ADT_L1_A429_PECSR_BITFAIL_INT		0x20000000
#define		ADT_L1_A429_PECSR_RUNIBIT			0x40000000
#define		ADT_L1_A429_PECSR_DEVICE_RESET		0x80000000
#define ADT_L1_A429_PE_ROOT_STS			0x0004
#define		ADT_L1_A429_PESTS_INTPND		0x00000001
#define		ADT_L1_A429_PESTS_IRIGDET		0x00000400
#define		ADT_L1_A429_PESTS_IRIGLOCK		0x00000800
#define		ADT_L1_A429_PESTS_LOOPFAIL		0x00002000
#define		ADT_L1_A429_PESTS_BITTIMEMASK	0x001F0000
#define		ADT_L1_A429_PESTS_FR_EN			0x04000000
#define		ADT_L1_A429_PESTS_SC_EN			0x08000000
#define ADT_L1_A429_PE_ROOT_IDVER		ADT_L1_PE_ROOT_IDVER
#define ADT_L1_A429_PE_TXRX_CHANCONFIG	0x000C
#define ADT_L1_A429_PE_RXP_CNTR			0x0014
#define ADT_L1_A429_PE_TXP_CNTR			0x0018
#define ADT_L1_A429_PE_TIMEHIGH			0x001C
#define ADT_L1_A429_PE_TIMELOW			0x0020
#define ADT_L1_A429_PE_IRIGTIMEHIGH		0x0024
#define ADT_L1_A429_PE_IRIGTIMELOW		0x0028
#define ADT_L1_A429_PE_BITSTATUS		ADT_L1_PE_BITSTATUS
#define		ADT_L1_A429_BIT_MEMTESTFAIL		0x00000002
#define		ADT_L1_A429_BIT_PROCFAIL		0x00000004
#define		ADT_L1_A429_BIT_TTAGFAIL		0x00000008
#define		ADT_L1_A429_BIT_POSTFAIL		0x01000000
#define		ADT_L1_A429_BIT_PBITFAIL		0x02000000
#define		ADT_L1_A429_BIT_IBITFAIL		0x04000000
#define		ADT_L1_A429_BIT_POSTINPROG		0x10000000
#define		ADT_L1_A429_BIT_PBITINPROG		0x20000000
#define		ADT_L1_A429_BIT_IBITINPROG		0x40000000
#define ADT_L1_A429_PE_INUSE			ADT_L1_PE_INUSE
#define ADT_L1_A429_PE_SC_CSR_RX1		0x0034
#define ADT_L1_A429_PE_SC_DATA_RX1		0x0038
#define ADT_L1_A429_PE_SC_CSR_RX2		0x003C
#define ADT_L1_A429_PE_SC_DATA_RX2		0x0040
#define		ADT_L1_A429_PE_SC_CSR_DATARDY		0x80000000
#define		ADT_L1_A429_PE_SC_CSR_FIFONOTEMPTY	0x40000000
#define		ADT_L1_A429_PE_SC_CSR_TRG_ANYACT	0x00000001
#define ADT_L1_A429_PE_INTVLTMR			0x004C
#define		ADT_L1_A429_PE_INTVLTMR_STARTSTOP	0x00000001
#define		ADT_L1_A429_PE_INTVLTMR_STARTONTRIG	0x00000002
#define		ADT_L1_A429_PE_INTVLTMR_EXTTRIG		0x00000008
#define		ADT_L1_A429_PE_INTVLTMR_SETINT		0x00000010
#define		ADT_L1_A429_PE_INTVLTMR_TIMECOMP	0x00000080
#define		ADT_L1_A429_PE_INTVLTMR_TIME24		0xFFFFFF00
#define		ADT_L1_A429_PE_INTVLTMR_TIMESHIFT	8
#define ADT_L1_A429_PE_MCRXP_DATATBLPTR	0x0080
#define ADT_L1_A429_PE_INTPENDING		0x00E0
#define ADT_L1_A429_PE_PB_1ST_TIME_HIGH 0x00F8
#define ADT_L1_A429_PE_PB_1ST_TIME_LOW  0x00FC

/* A429 Root Interrupt Registers */
/* *** AltaCore-ARINC: Interrupt Functions *** */
#define ADT_L1_A429_IQ_START_IQP		0x0100
#define ADT_L1_A429_IQ_CURR_IQP			0x0104
#define ADT_L1_A429_IQ_SEQNUM			0x0108
#define ADT_L1_A429_IQ_RESV_API			0x012C

/* A429 Root Signal Generator (SG) Registers */
/* *** AltaCore-ARINC: Signal Generator *** */
#define ADT_L1_A429_ROOT_SG_REGS		0x0130
#define ADT_L1_A429_SGREG_1ST_SGCB_PTR	0x0130
#define ADT_L1_A429_SGREG_CUR_SGCB_PTR	0x0134
#define ADT_L1_A429_SGREG_USER_COUNTER	0x0138
#define ADT_L1_A429_SGREG_PE_COUNTER	0x013C
#define ADT_L1_A429_SGREG_PE_OFFSET		0x0140

/* A429 SG Control Block Offsets (BYTE offsets) */
/* *** AltaCore-ARINC: Signal Generator *** */
#define ADT_L1_A429_SGCB_NEXTPTR	0x0000
#define ADT_L1_A429_SGCB_CSR		0x0004
#define ADT_L1_A429_SGCB_TIMEHIGH	0x0008
#define ADT_L1_A429_SGCB_TIMELOW	0x000C
#define ADT_L1_A429_SGCB_VECCOUNT	0x0010
#define ADT_L1_A429_SGCB_VECTORS	0x0014

/* A429 SG Vector Constants */
/* *** AltaCore-ARINC: Signal Generator *** */
#define ADT_L1_A429_SG_VECTOR_GND0	0
#define ADT_L1_A429_SG_VECTOR_LOW	1
#define ADT_L1_A429_SG_VECTOR_HIGH	2
#define ADT_L1_A429_SG_VECTOR_GND1	3

/* A429 Root Receive (RX) Registers */
/* *** AltaCore-ARINC: Receive (RX) *** */
#define ADT_L1_A429_ROOT_RX_REGS		0x0200
#define		ADT_L1_A429_RXREG_CHAN_SIZE		0x0040
#define		ADT_L1_A429_RXREG_SETUP1		0x0000
#define			ADT_L1_A429_RXREG_SETUP1_RXON		0x00000001
#define			ADT_L1_A429_RXREG_SETUP1_MCRX		0x00000002
#define			ADT_L1_A429_RXREG_SETUP1_717SYNCON	0x00000004
#define			ADT_L1_A429_RXREG_SETUP1_MSB1ST		0x00000008
#define			ADT_L1_A429_RXREG_SETUP1_PARITYODD	0x00000010
#define			ADT_L1_A429_RXREG_SETUP1_PARITYON	0x00000020
#define			ADT_L1_A429_RXREG_SETUP1_MODEBITS	6
#define			ADT_L1_A429_RXREG_SETUP1_ZEROBITDEF	8
#define			ADT_L1_A429_RXREG_SETUP1_ONEBITDEF	12
#define			ADT_L1_A429_RXREG_SETUP1_HLFBITRATE	16
#define			ADT_L1_A429_RXREG_SETUP1_BPW		26
#define		ADT_L1_A429_RXREG_SETUP2		0x0004
#define		ADT_L1_A429_RXREG_RXPCNT		0x0008
#define		ADT_L1_A429_RXREG_DATATBLPTR	0x000C
#define		ADT_L1_A429_RXREG_MASK1			0x0010
#define		ADT_L1_A429_RXREG_COMPARE1		0x0014
#define		ADT_L1_A429_RXREG_MASK2			0x0018
#define		ADT_L1_A429_RXREG_COMPARE2		0x001C
#define		ADT_L1_A429_RXREG_LABELCVTPTR	0x0028
#define		ADT_L1_A717_RXREG_CSR			0x002C
#define			ADT_L1_A429_A717_RXREG_CSR_LOCK		0x80000000
#define		ADT_L1_A717_RXREG_SYNC1			0x0030
#define		ADT_L1_A717_RXREG_SYNC2			0x0034
#define		ADT_L1_A717_RXREG_SYNC3			0x0038
#define		ADT_L1_A717_RXREG_SYNC4			0x003C

/* A429 API Init Option Values for ADT_L1_A429_RX_Channel_Init() */
#define		ADT_L1_A429_API_RX_MCON			0x00000001
#define		ADT_L1_A429_API_RX_LABELCVTON	0x00000002

/* A429 Root Transmit (TX) Registers */
/* *** AltaCore-ARINC: Transmit (TX) *** */
#define ADT_L1_A429_ROOT_TX_REGS		0x0800
#define		ADT_L1_A429_TXREG_CHAN_SIZE		0x0040
#define		ADT_L1_A429_TXREG_1ST_TXCB_PTR	0x0000
#define		ADT_L1_A429_TXREG_CUR_TXCB_PTR	0x0004
#define		ADT_L1_A429_TXREG_TX_CSR1		0x0008
#define			ADT_L1_A429_TXREG_TX_CSR1_START			0x00000001
#define			ADT_L1_A429_TXREG_TX_CSR1_STOPPED		0x00000002
#define			ADT_L1_A429_TXREG_TX_CSR1_PBMODE		0x00000010
#define			ADT_L1_A429_TXREG_TX_CSR1_PB_WAITFORTRG	0x00000020
#define			ADT_L1_A429_TXREG_TX_CSR1_INTONTXSTOP	0x00004000
#define		ADT_L1_A429_TXREG_TX_CSR2		0x000C
#define			ADT_L1_A429_TXREG_TX_CSR2_MSB1ST		0x00000008
#define			ADT_L1_A429_TXREG_TX_CSR2_717MODE		0x00000010
#define			ADT_L1_A429_TXREG_TX_CSR2_HISLEWRATE	0x00000020
#define			ADT_L1_A429_TXREG_TX_CSR2_MODEBITS		6
#define			ADT_L1_A429_TXREG_CSR2_ZEROBITDEF		8
#define			ADT_L1_A429_TXREG_CSR2_ONEBITDEF		12
#define			ADT_L1_A429_TXREG_CSR2_HLFBITRATE		16
#define			ADT_L1_A429_TXREG_CSR2_BPW				26
#define		ADT_L1_A429_TXREG_TXP_COUNT		0x0010
#define     ADT_L1_A429_TXREG_APERIODIC_TXP 0x0014
#define			ADT_L1_A429_APIAPERIODICSET				0x04000000
#define		ADT_L1_A429_TXREG_API_TXCB_PTR  0x0018
#define		ADT_L1_A429_TXREG_API_TXCB_SIZE	0x001C
#define		ADT_L1_A429_TXREG_API_TAILPTR	0x0024  /* v3.0.1.2 changed from 0x20 to 0x24, Jake was using 0x20 */

/* A429 RX SETUP1 MODEBITS Values */
/* *** AltaCore-ARINC: Receive (RX) *** */
#define	ADT_L1_A429_RXREG_SETUP1_MODEBITS_429PHY	0
#define	ADT_L1_A429_RXREG_SETUP1_MODEBITS_5VRAW		1
#define	ADT_L1_A429_RXREG_SETUP1_MODEBITS_5V717		2

/* A429 TX CSR2 MODEBITS Values */
/* *** AltaCore-ARINC: Transmit (TX) *** */
#define	ADT_L1_A429_TXREG_SETUP1_MODEBITS_429PHY	0
#define	ADT_L1_A429_TXREG_SETUP1_MODEBITS_5V717		2


/******* A429 Extended Memory Definitions and Data Structure Offsets (Byte Offsets) *******/
/* API Number of Labels per ARINC Word (first 8 bits of word) */
#define ADT_L1_A429_API_NUMOF429LABELS		256

/* A429 Receive Packet (RXP) Offsets (BYTE offsets) */
/* *** AltaCore-ARINC: Receive (RX) *** */
#define ADT_L1_A429_RXP_SIZE		0x0010
#define ADT_L1_1553_RXP_WRDCNT		4
#define		ADT_L1_A429_RXP_CONTROL				0x0000
#define			ADT_L1_A429_RXP_CONTROL_TRGOUT		0x20000000
#define			ADT_L1_A429_RXP_CONTROL_INTERRUPT	0x40000000
#define			ADT_L1_A429_RXP_CONTROL_DECERROR	0x80000000
#define		ADT_L1_A429_RXP_TIMEHIGH			0x0004
#define		ADT_L1_A429_RXP_TIMELOW 			0x0008
#define		ADT_L1_A429_RXP_DATA				0x000C

/* A429 RXP Data Table Offsets (BYTE offsets) */
/* *** AltaCore-ARINC: Receive (RX) *** */
#define ADT_L1_A429_RXP_HDR_SIZE	0x0010
#define		ADT_L1_A429_RXP_HDR_TOTAL_RXPCNT	0x0000
#define		ADT_L1_A429_RXP_HDR_CURRENT_RXPCNT	0x0004
#define		ADT_L1_A429_RXP_HDR_API_TAIL_INDEX	0x000C

/* A429 Transmit (TX) Control Block Offsets (BYTE offsets */
/* *** AltaCore-ARINC: Transmit (TX) *** */
#define ADT_L1_A429_TXCB_SIZE		0x0040
#define		ADT_L1_A429_TXCB_NEXTPTR			0x0000
#define			ADT_L1_A429_TXCB_NO_NEXT_TXCB			0xFFFFFFFF
#define		ADT_L1_A429_TXCB_TXTIMEVALUE		0x0004
#define		ADT_L1_A429_TXCB_TXTIMEINCREMENT	0x0008
#define		ADT_L1_A429_TXCB_CONTROL			0x000C
#define			ADT_L1_A429_TXCB_CONTROL_STOPONTXBCOMP	0x00000010
#define			ADT_L1_A429_TXCB_CONTROL_INTONTXBCOMP	0x00000100
#define		ADT_L1_A429_TXCB_TXPPTR				0x0010
#define		ADT_L1_A429_TXCB_TXPCOUNT			0x0014
#define		ADT_L1_A429_TXCB_PECOUNT			0x0018
#define		ADT_L1_A429_TXCB_APITXCBNUM			0x002C
#define		ADT_L1_A429_TXCB_APINUMTXPS			0x0030
#define		ADT_L1_A429_TXCB_API1STTXPPTR		0x0034

/* A429 Transmit Packet (TXP) Offsets (BYTE offsets) */
/* *** AltaCore-ARINC: Transmit (TX) *** */
#define ADT_L1_A429_TXP_SIZE		0x0010
#define		ADT_L1_A429_TXP_CONTROL				0x0000
#define			ADT_L1_A429_TXP_CONTROL_DELAYONLY		0x00000001
#define			ADT_L1_A429_TXP_CONTROL_TRIGIN			0x00000002
#define			ADT_L1_A429_TXP_CONTROL_TRIGOUT			0x00000004
#define			ADT_L1_A429_TXP_CONTROL_INTERRUPT		0x00000008
#define			ADT_L1_A429_TXP_CONTROL_PARITYODD		0x00000010
#define			ADT_L1_A429_TXP_CONTROL_PARITYON		0x00000020
#define		ADT_L1_A429_TXP_RESERVED			0x0004
#define		ADT_L1_A429_TXP_DELAY				0x0008
#define		ADT_L1_A429_TXP_DATA				0x000C

/* A429 Playback (PB) Control Block Offsets (BYTE offsets */
/* *** AltaCore-ARINC: Playback (PB) *** */
#define ADT_L1_A429_PBCB_SIZE		0x0040
#define		ADT_L1_A429_PBCB_NEXTPTR			0x0000
#define			ADT_L1_A429_PBCB_NO_NEXT_PBCB			0xFFFFFFFF
#define		ADT_L1_A429_PBCB_CONTROL			0x000C
#define			ADT_L1_A429_PBCB_CONTROL_STOPONPBCBCOMP	0x00000010
#define			ADT_L1_A429_PBCB_CONTROL_INTONPBCBCOMP	0x00000100
#define		ADT_L1_A429_PBCB_PXPPTR				0x0010
#define		ADT_L1_A429_PBCB_PXPCOUNT			0x0014
#define		ADT_L1_A429_PBCB_PECOUNT			0x0018
#define		ADT_L1_A429_PBCB_APIPBCBNUM			0x002C
#define		ADT_L1_A429_PBCB_APINUMPXPS			0x0030
#define		ADT_L1_A429_PBCB_API1STPBPPTR		0x0034

/* A429 Playback: API Option Bit for ADT_L1_A429_PB_RXPWrite() */
#define		ADT_L1_A429_PB_API_ATON				0x80000000

/* A429 Playback Transmit Packet (PXP) Offsets (BYTE offsets) */
/* *** AltaCore-ARINC: Playback (PB) *** */
#define ADT_L1_A429_PXP_SIZE		0x0010
#define		ADT_L1_A429_PXP_CONTROL				0x0000
#define		ADT_L1_A429_PXP_TIMEHIGH			0x0004
#define		ADT_L1_A429_PXP_TIMELOW 			0x0008
#define		ADT_L1_A429_PXP_DATA				0x000C

/* A429 Interrupt Offsets (BYTE offsets) */
/* *** AltaCore-ARINC: Interrupt Functions *** */
#define	ADT_L1_A429_IQP_NEXTPTR 0x0000
#define	ADT_L1_A429_IQP_TYPESEQ 0x0004
#define		ADT_L1_A429_IQP_TYPESEQ_SEQNUM	0x000000FF
#define		ADT_L1_A429_IQP_TYPESEQ_CHNUM	0x00000F00
#define		ADT_L1_A429_IQP_TYPESEQ_SG		0x00010000
#define		ADT_L1_A429_IQP_TYPESEQ_CVTRXP	0x00020000
#define		ADT_L1_A429_IQP_TYPESEQ_BIT		0x00100000
#define     ADT_L1_A429_IQP_TYPESEQ_INTVLTMR 0x00200000
#define		ADT_L1_A429_IQP_TYPESEQ_TXPBCB	0x02000000
#define		ADT_L1_A429_IQP_TYPESEQ_TXPBSTOP 0x08000000
#define		ADT_L1_A429_IQP_TYPESEQ_TXPBXP	0x10000000
#define		ADT_L1_A429_IQP_TYPESEQ_MCRXP	0x20000000
#define		ADT_L1_A429_IQP_TYPESEQ_CHRXP	0x40000000
#define		ADT_L1_A429_IQP_TYPESEQ_MSKRXP	0x80000000
#define	ADT_L1_A429_IQP_DSPTR	0x0008


/*********************************************/
/************* WMUX and EBR1553 **************/
#define ADT_L1_WMUX_CHAN_REGS		0x0000
#define ADT_L1_EBR1553_CHAN_REGS	0x0000


/*********************************************/
/********** Memory Sizes (in BYTES) **********/
#define ADT_L1_SIM1553_CHAN_SIZE		0x100000	/* SIM-1553 Board */
#define ADT_L1_TEST1553_CHAN_SIZE		0x080000	/* TEST-1553 Board */
#define ADT_L1_PMC1553_CHAN_SIZE		0x100000	/* PMC-1553 Board */
#define ADT_L1_PCI1553_CHAN_SIZE		0x100000	/* PCI-1553 Board */
#define ADT_L1_PC104P1553_CHAN_SIZE		0x100000	/* PC104P-1553 Board */
#define ADT_L1_PCCD1553_CHAN_SIZE		0x100000	/* PCCD-1553 Board */
#define ADT_L1_PCI104E1553_CHAN_SIZE	0x100000	/* PCI104E-1553 Board */
#define ADT_L1_XMCE4L1553_CHAN_SIZE		0x100000	/* XMCE4L-1553 Board */
#define ADT_L1_ECD54_1553_CHAN_SIZE		0x100000	/* ECD54-1553 Board */
#define ADT_L1_PCIE4L1553_CHAN_SIZE		0x100000	/* PCIE4L-1553 Board */
#define ADT_L1_PCIE1L1553_CHAN_SIZE		0x100000	/* PCIE1L-1553 Board */
#define ADT_L1_MPCIE1553_CHAN_SIZE		0x100000	/* MPCIE-1553 Board */
#define ADT_L1_XMCMW_CHAN_SIZE			0x100000	/* XMC-MW Board */

#define ADT_L1_SIMA429_CHAN_SIZE		0x100000	/* SIM-A429 Board */
#define ADT_L1_TESTA429_CHAN_SIZE		0x100000	/* TEST-A429 Board */
#define ADT_L1_PMCA429_CHAN_SIZE		0x100000	/* PMC-A429 Board */
#define ADT_L1_PCIA429_CHAN_SIZE		0x100000	/* PCI-A429 Board */
#define ADT_L1_PC104PA429_CHAN_SIZE		0x100000	/* PC104P-A429 Board */
#define ADT_L1_PC104PA429LTV_CHAN_SIZE	0x100000	/* PC104P-A429 Board */
#define ADT_L1_PCCDA429_CHAN_SIZE		0x100000	/* PCCD-A429 Board */
#define ADT_L1_PCI104EA429_CHAN_SIZE	0x100000	/* PCI104E-A429 Board */
#define ADT_L1_XMCE4LA429_CHAN_SIZE		0x100000	/* XMCE4L-A429 Board */
#define ADT_L1_ECD54_A429_CHAN_SIZE		0x100000	/* ECD54-A429 Board */
#define ADT_L1_PCIE4LA429_CHAN_SIZE		0x100000	/* PCIE4L-A429 Board */
#define ADT_L1_PCIE1LA429_CHAN_SIZE		0x100000	/* PCIE1L-A429 Board */
#define ADT_L1_MPCIEA429_CHAN_SIZE		0x100000	/* MPCIE-A429 Board */
#define ADT_L1_XMCA429_CHAN_SIZE		0x100000	/* XMC-A429 Board */

#define ADT_L1_PMCMA4_CHAN_SIZE			0x080000	/* PMC-MA4 1553/ARINC Board */
#define ADT_L1_PC104PMA4_CHAN_SIZE		0x100000	/* PC104P-MA4 1553/ARINC Board */
#define ADT_L1_PC104EMA4_CHAN_SIZE		0x100000	/* PC104E-MA4 1553/ARINC Board */
#define ADT_L1_XMCMA4_CHAN_SIZE			0x080000	/* XMC-MA4 1553/ARINC Board */

#define ADT_L1_ENET1553_CHAN_SIZE		0x100000	/* ENET-1553 Device */
#define ADT_L1_PMCE1553_CHAN_SIZE		0x100000	/* PMCE-1553 Device */
#define ADT_L1_ENETA429_CHAN_SIZE		0x100000	/* ENET-A429 Device */
#define ADT_L1_ENETA429P_CHAN_SIZE		0x100000	/* ENET-A429P Device */
#define ADT_L1_ENET1A1553_CHAN_SIZE		0x100000	/* ENET1A-1553 Device */
#define ADT_L1_ENET485_CHAN_SIZE		0x100000	/* ENET-485 Device */
#define ADT_L1_ENET2_1553_CHAN_SIZE		0x100000	/* ENET2-1553 Device */
#define ADT_L1_ENET_MA4_CHAN_SIZE		0x100000	/* ENET-MA4 Device */
#define ADT_L1_ENETX_MA4_CHAN_SIZE		0x100000	/* ENETX-MA4 Device */

#define ADT_L1_PMCWMUX_CHAN_SIZE		0x100000	/* PMC-WMUX Board */


/* *** AltaCore-1553 Manual - General Data Structure Byte Sizes *** */
#define ADT_L1_1553_USER_MEM_START	0x1000
#define ADT_L1_1553_CDP_SIZE		0x00C4
#define ADT_L1_1553_IQ_ENTRY_SIZE	0x0014
#define ADT_L1_1553_RT_CB_SIZE		0x0010
#define	ADT_L1_1553_RT_FT_SIZE		0x0200
#define	ADT_L1_1553_RT_SA_CB_SIZE	0x0010
#define ADT_L1_1553_BC_CB_SIZE		0x0040
#define ADT_L1_1553_PB_PKT_SIZE		0x011C      /* Max size for 1553 PB packet (63 words + header) */

/* *** AltaCore-ARINC Manual - General Data Structure Byte Sizes *** */
#define ADT_L1_A429_USER_MEM_START	0x1000
#define ADT_L1_A429_IQ_ENTRY_SIZE	0x0010

/********* Layer 1 Error Codes (1000 to 1999) *********/
#define ADT_ERR_BAD_INPUT			1000		/*!< \brief Bad input parameters. */
#define ADT_ERR_MEM_TEST_FAIL		1001		/*!< \brief Failed memory test. */
#define ADT_ERR_MEM_MGT_NO_INIT		1002		/*!< \brief Memory Management not initialized for the device ID */
#define ADT_ERR_MEM_MGT_INIT		1003		/*!< \brief Memory Management already initialized for the device ID */
#define ADT_ERR_MEM_MGT_NO_MEM		1004		/*!< \brief Not enough memory available */
#define ADT_ERR_BAD_DEV_TYPE		1005		/*!< \brief Bad device type in device ID */
#define ADT_ERR_RT_FT_UNDEF			1006		/*!< \brief RT Filter Table not defined */
#define ADT_ERR_RT_SA_UNDEF			1007		/*!< \brief RT Subaddress not defined */
#define ADT_ERR_RT_SA_CDP_UNDEF		1008		/*!< \brief RT SA CDP not defined */
#define ADT_ERR_IQ_NO_NEW_ENTRY		1009		/*!< \brief No new entry in interrupt queue */
#define ADT_ERR_NO_BCCB_TABLE		1010		/*!< \brief BCCB Table Pointer is zero */
#define ADT_ERR_BCCB_ALREADY_ALLOCATED 1011		/*!< \brief BCCB already allocated */
#define ADT_ERR_BCCB_NOT_ALLOCATED	1012		/*!< \brief BCCB has not been allocated */
#define ADT_ERR_BUFFER_FULL			1013		/*!< \brief 1553-ARINC PB (CDP/PCB or RXP/PXP) buffer is full */
#define ADT_ERR_TIMEOUT				1014		/*!< \brief Timeout error. */
#define ADT_ERR_BAD_CHAN_NUM		1015		/*!< \brief Bad channel number or channel does not exist on this board */
#define ADT_ERR_BITFAIL				1016		/*!< \brief Built-In Test failure */
#define ADT_ERR_DEVICEINUSE			1017		/*!< \brief Device in use already */
#define ADT_ERR_NO_TXCB_TABLE		1018		/*!< \brief TXCB Table Pointer is zero */
#define ADT_ERR_TXCB_ALREADY_ALLOCATED 1019		/*!< \brief TXCB already allocated */
#define ADT_ERR_TXCB_NOT_ALLOCATED	1020		/*!< \brief TXCB has not been allocated */
#define ADT_ERR_PBCB_TOOMANYPXPS	1021		/*!< \brief PBCB Too Many PXPs For PCBC Allocation */
#define ADT_ERR_NORXCHCVT_ALLOCATED 1022		/*!< \brief RX CH - No CVT Option Defined at Init */
#define ADT_ERR_NO_DATA_AVAILABLE   1023		/*!< \brief No Data Available */

/********** ENET-1553 APMP Definitions ***********/
#define	ADT_ENET1553_APMP_BYTECNT	228
#define	ADT_ENET1553_APMP_MODE		0x0000
#define	ADT_ENET1553_APMP_STS		0x0008
#define		ADT_ENET1553_APMP_STS_1553BIT	0x00010000
#define		ADT_ENET1553_APMP_STS_A429BIT	0x00020000
#define	ADT_ENET1553_APMP_PLSIZE	0x001C
#define	ADT_ENET1553_APMP_CDPSTART	0x0020

/********** Type Definitions **********/
/*! \brief 1553 BC/RT/BM CDP structure */
/* *** AltaCore-1553 Manual: Common Data Packet (CDP) *** */
typedef struct adt_l1_1553_cdp {
	ADT_L0_UINT32 NextPtr;						/*!< \brief CDP next pointer */
	ADT_L0_UINT32 BMCount;						/*!< \brief BM message count */
	ADT_L0_UINT32 APIinfo;						/*!< \brief Reserved for API */
	ADT_L0_UINT32 Rsvd1;						/*!< \brief Reserved */
	ADT_L0_UINT32 Rsvd2;						/*!< \brief Reserved */
	ADT_L0_UINT32 MaskValue;					/*!< \brief Mask value */
	ADT_L0_UINT32 MaskCompare;					/*!< \brief Mask compare value */
	ADT_L0_UINT32 CDPControlWord;				/*!< \brief CDP control word */
	ADT_L0_UINT32 CDPStatusWord;				/*!< \brief CDP status word */
	ADT_L0_UINT32 TimeHigh;						/*!< \brief Timestamp, upper 32-bits */
	ADT_L0_UINT32 TimeLow;						/*!< \brief Timestamp, lower 32-bits */
	ADT_L0_UINT32 IMGap;						/*!< \brief Intermessage gap, 100ns LSB */
	ADT_L0_UINT32 Rsvd3;						/*!< \brief Reserved */
	ADT_L0_UINT32 CMD1info;						/*!< \brief Command 1 info */
	ADT_L0_UINT32 CMD2info;						/*!< \brief Command 2 info */
	ADT_L0_UINT32 STS1info;						/*!< \brief Status 1 info */
	ADT_L0_UINT32 STS2info;						/*!< \brief Status 2 info */
	ADT_L0_UINT32 DATAinfo[32];					/*!< \brief Data word info */
} ADT_L1_1553_CDP;

/*! \brief 1553 BC Control Block structure */
/* *** AltaCore-1553 Manual: Bus Controller (BC) *** */
typedef struct adt_l1_1553_bc_cb {
	ADT_L0_UINT32 NextMsgNum;					/*!< \brief Next message number */
	ADT_L0_UINT32 Retry;						/*!< \brief BC Retry word */
	ADT_L0_UINT32 Csr;							/*!< \brief BC CB CSR */
	ADT_L0_UINT32 CMD1Info;						/*!< \brief Command word 1 info */
	ADT_L0_UINT32 CMD2Info;						/*!< \brief Command word 2 info */
	ADT_L0_UINT32 FrameTime;					/*!< \brief Frame time, 100ns LSB, applies if start of frame */
	ADT_L0_UINT32 DelayTime;					/*!< \brief Delay time, 100ns LSB, IM gap or delay from SOF */
	ADT_L0_UINT32 BranchMsgNum;					/*!< \brief Branch message number */
	ADT_L0_UINT32 StartFrame;					/*!< \brief Start frame number */
	ADT_L0_UINT32 StopFrame;					/*!< \brief Stop frame number */
	ADT_L0_UINT32 FrameRepRate;					/*!< \brief Frame repitition rate */
	ADT_L0_UINT32 MsgNum;						/*!< \brief Message number for this BCCB */
	ADT_L0_UINT32 NumBuffers;					/*!< \brief Number of CDPs allocated to this BCCB */
} ADT_L1_1553_BC_CB;

/*! \brief 1553 Interrupt structure */
/* *** AltaCore-1553: Interrupt Functions *** */
typedef struct adt_l1_1553_int {
	ADT_L0_UINT32 NextPtr;						/*!< \brief IQ next pointer */
	ADT_L0_UINT32 Type_SeqNum;					/*!< \brief IQ Type */
	ADT_L0_UINT32 IntData;						/*!< \brief IQ Data */
} ADT_L1_1553_INT;

/*! \brief A429 Receive Packet structure */
/* *** AltaCore-ARINC: Receive (RX) *** */
typedef struct adt_l1_a429_rxp {
	ADT_L0_UINT32 Control;						/*!< \brief Control Word */
	ADT_L0_UINT32 TimeHigh;						/*!< \brief Timestamp, upper 32-bits */
	ADT_L0_UINT32 TimeLow;						/*!< \brief Timestamp, lower 32-bits */
	ADT_L0_UINT32 Data;							/*!< \brief ARINC word */
} ADT_L1_A429_RXP;

/*! \brief A429 Transmit Packet structure */
/* *** AltaCore-ARINC: Transmit (TX) *** */
typedef struct adt_l1_a429_txp {
	ADT_L0_UINT32 Control;						/*!< \brief Control Word */
	ADT_L0_UINT32 Reserved;						/*!< \brief Reserved Word */
	ADT_L0_UINT32 Delay;						/*!< \brief Delay Word (100ns LSB) */
	ADT_L0_UINT32 Data;							/*!< \brief ARINC word */
} ADT_L1_A429_TXP;

/*! \brief A429 Transmit Control Block structure */
/* *** AltaCore-ARINC: Transmit (TX) *** */
typedef struct adt_l1_a429_txcb {
	ADT_L0_UINT32 TxcbNum;						/*!< \brief TXCB number */
	ADT_L0_UINT32 NextTxcbNum;					/*!< \brief Next TXCB number */
	ADT_L0_UINT32 Control;						/*!< \brief Control Word */
	ADT_L0_UINT32 TotalTxpCount;				/*!< \brief Number of TxP for this block */
	ADT_L0_UINT32 CurrTxpIndex;					/*!< \brief Index to current TxP */
	ADT_L0_UINT32 TxPeriod500us;				/*!< \brief TX Period, 500us LSB */
} ADT_L1_A429_TXCB;

/*! \brief A429 Interrupt structure */
/* *** AltaCore-ARINC: Interrupt Functions *** */
typedef struct adt_l1_A429_int {
	ADT_L0_UINT32 NextPtr;						/*!< \brief IQ next pointer */
	ADT_L0_UINT32 Type_SeqNum;					/*!< \brief IQ Type */
	ADT_L0_UINT32 IntData;						/*!< \brief IQ Data */
} ADT_L1_A429_INT;


/**************************************************/
/********** Exported Function Prototypes **********/
/* *** See AltaAPI Manual for Further Descriptions *** */

/* General */
char * ADT_L0_CALL_CONV ADT_L1_Error_to_String(ADT_L0_UINT32 err_status);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_ENET_SetIpAddr(ADT_L0_UINT32 devID, 
												     ADT_L0_UINT32 ServerIpAddr, 
												     ADT_L0_UINT32 ClientIpAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_ENET_GetIpAddr(ADT_L0_UINT32 devID, 
												     ADT_L0_UINT32 *pServerIpAddr, 
												     ADT_L0_UINT32 *pClientIpAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_ENET_ADCP_Reset(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_ENET_ADCP_GetStatistics(ADT_L0_UINT32 devID, 
															  ADT_L0_UINT32 *pPortNum, 
															  ADT_L0_UINT32 *pTransactions, 
															  ADT_L0_UINT32 *pRetries, 
															  ADT_L0_UINT32 *pFailures);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_ENET_ADCP_ClearStatistics(ADT_L0_UINT32 devID);

ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_DevicePresent(ADT_L0_UINT32 devID,
													ADT_L0_UINT32 *config,
													ADT_L0_UINT32 *serNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_DevicePresent_pciInfo(ADT_L0_UINT32 devID, 
															ADT_L0_UINT32 *config, 
															ADT_L0_UINT32 *serNum, 
															ADT_L0_UINT32 *pciBus, 
															ADT_L0_UINT32 *pciDevice, 
															ADT_L0_UINT32 *pciFunc);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_InitDevice(ADT_L0_UINT32 devID,
												 ADT_L0_UINT32 startupOptions);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_CloseDevice(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_GetVersionInfo(ADT_L0_UINT32 devID,
									ADT_L0_UINT16 *peVersion,
									ADT_L0_UINT32 *layer0ApiVersion,
									ADT_L0_UINT32 *layer1ApiVersion);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_GetBoardInfo(ADT_L0_UINT32 devID,
									ADT_L0_UINT32 *prodIDandRev,
									ADT_L0_UINT32 *capabilitiesReg,
									ADT_L0_UINT32 *serialNumber,
									ADT_L0_UINT32 *alignCheck,
									ADT_L0_UINT32 *memorySize);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_ReadDeviceMem32(ADT_L0_UINT32 devID,
									 ADT_L0_UINT32 offset,
									 ADT_L0_UINT32 *pData,
									 ADT_L0_UINT32 count);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_WriteDeviceMem32(ADT_L0_UINT32 devID,
									  ADT_L0_UINT32 offset,
									  ADT_L0_UINT32 *pData,
									  ADT_L0_UINT32 count);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_ProgramBoardFlash(ADT_L0_UINT32 devID,
									   ADT_L0_UINT32 numBytes,
									   ADT_L0_UINT8 * fpga_load_bytes);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_msSleep(ADT_L0_UINT32 milliSecTick);


/***** Internal Functions ******/
ADT_L0_UINT32 ADT_L0_CALL_CONV Internal_GetChannelRegOffset(ADT_L0_UINT32 devID,
										   ADT_L0_UINT32 *pChannel,
										   ADT_L0_UINT32 *pChannelRegOffset);

/* Globals */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_TimeClear(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_ConfigExtClk(ADT_L0_UINT32 devID,
														  ADT_L0_UINT32 clkFreq,
														  ADT_L0_UINT32 clkSrcIn,
														  ADT_L0_UINT32 clkSrcOut);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_I2C_ReadTemp(ADT_L0_UINT32 devID,
														ADT_L0_UINT32 temp_addr,
														ADT_L0_UINT32 *temp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_I2C_SetIrigDac(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 value);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_I2C_SetVVDac(ADT_L0_UINT32 devID,
														  ADT_L0_UINT32 channel,
														  ADT_L0_UINT32 value);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_ReadIrigTime(ADT_L0_UINT32 devID,
														  ADT_L0_UINT32 *irigHigh,
														  ADT_L0_UINT32 *irigLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_CalibrateIrigDac(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_Global_CalibrateIrigDacOptions(ADT_L0_UINT32 devID, ADT_L0_UINT32 options);

/* Memory Management */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_InitMemMgmt(ADT_L0_UINT32 devID,
												  ADT_L0_UINT32 startupOptions);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_CloseMemMgmt(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_MemoryAlloc(ADT_L0_UINT32 devID,
								 ADT_L0_UINT32 memSize,
								 ADT_L0_UINT32 *pMemOffset);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_MemoryFree(ADT_L0_UINT32 devID,
								ADT_L0_UINT32 memStart,
								ADT_L0_UINT32 memSize);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_GetMemoryAvailable(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 *memAvailable);

/* BIT */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_BIT_MemoryTest(ADT_L0_UINT32 devID,
									   ADT_L0_UINT32 start,
									   ADT_L0_UINT32 end,
									   ADT_L0_UINT32 *addr,
									   ADT_L0_UINT32 *exp,
									   ADT_L0_UINT32 *act);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_BIT_InitiatedBIT(ADT_L0_UINT32 devID,
													  ADT_L0_UINT32 *bitStatus);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_BIT_PeriodicBIT(ADT_L0_UINT32 devID,
													  ADT_L0_UINT32 *bitStatus);

/* Interrupts */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_INT_HandlerAttach(ADT_L0_UINT32 devID,
									   ADT_L0_PUSERISR pUserISR, 
									   void * pUserData);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_INT_HandlerDetach(ADT_L0_UINT32 devID);

/********** 1553 Functions **********/
/* 1553 General */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_InitDefault(ADT_L0_UINT32 devID,
									  ADT_L0_UINT32 numIQEntries);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_InitDefault_ExtendedOptions(ADT_L0_UINT32 devID,
																	   ADT_L0_UINT32 numIQEntries,
																	   ADT_L0_UINT32 startupOptions);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SetConfig(ADT_L0_UINT32 devID,
								 ADT_L0_UINT32 isMultRT,
								 ADT_L0_UINT32 is1553B,
								 ADT_L0_UINT32 isRt31Bcast,
								 ADT_L0_UINT32 useIntBus,
								 ADT_L0_UINT32 stsRespTimeout_us);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_GetConfig(ADT_L0_UINT32 devID,
									ADT_L0_UINT32 *pIsMultRT,
									ADT_L0_UINT32 *pIs1553B,
									ADT_L0_UINT32 *pIsRt31Bcast,
									ADT_L0_UINT32 *pUseIntBus,
								    ADT_L0_UINT32 *pStsRespTimeout_us);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_InitChannel(ADT_L0_UINT32 devID,
									  ADT_L0_UINT32 numIQEntries);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_InitChannelLive(ADT_L0_UINT32 devID,
									  ADT_L0_UINT32 numIQEntries);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_GetPEInfo(ADT_L0_UINT32 devID,
									ADT_L0_UINT32 *peInfo);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_TimeSet(ADT_L0_UINT32 devID,
								  ADT_L0_UINT32 timeHigh,
								  ADT_L0_UINT32 timeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_TimeGet(ADT_L0_UINT32 devID,
								  ADT_L0_UINT32 *pTimeHigh,
								  ADT_L0_UINT32 *pTimeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_TimeClear(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PBTimeSet(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 timeHigh,
													 ADT_L0_UINT32 timeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PBTimeGet(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 *pTimeHigh,
													 ADT_L0_UINT32 *pTimeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_UseExtClk(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 useExtClk,
													 ADT_L0_UINT32 clkFreq);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_ForceTrgOut(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SC_ArmTrigger(ADT_L0_UINT32 devID,
														 ADT_L0_UINT32 bus,
														 ADT_L0_UINT32 trigger,
														 ADT_L0_UINT32 mask_value);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SC_ReadBuffer(ADT_L0_UINT32 devID,
														 ADT_L0_UINT32 bus,
														 ADT_L0_UINT8 *buffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_CDP_Calculate_1760_Checksum(ADT_L1_1553_CDP *pCdp,
																	   ADT_L0_UINT32 wordCount,
																	   ADT_L0_UINT16 *pChecksum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_IntervalTimerGet(ADT_L0_UINT32 devID, 
															ADT_L0_UINT32 *pIntvlTmrReg);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_IntervalTimerSet(ADT_L0_UINT32 devID, 
															ADT_L0_UINT32 intvlTmrReg);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_IrigLatchedTimeGet(ADT_L0_UINT32 devID, 
															  ADT_L0_UINT32 *pIrigTimeHigh, ADT_L0_UINT32 *pIrigTimeLow, 
															  ADT_L0_UINT32 *pIntTimeHigh, ADT_L0_UINT32 *pIntTimeLow, 
															  ADT_L0_UINT32 *pDeltaTimeHigh, ADT_L0_UINT32 *pDeltaTimeLow);

/* 1553 Interrupt */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_EnableInt(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_DisableInt(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_GenInt(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_CheckChannelIntPending(ADT_L0_UINT32 devID,
												 ADT_L0_UINT32 *pIsIntPending);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_IQ_ReadEntry(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 *pType,
															ADT_L0_UINT32 *pInfo);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_IQ_ReadNewEntries(ADT_L0_UINT32 devID,
																ADT_L0_UINT32 maxNumEntries,
																ADT_L0_UINT32 *pNumEntries,
																ADT_L0_UINT32 *pType,
																ADT_L0_UINT32 *pInfo);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_IQ_ReadRawEntry(	ADT_L0_UINT32 devID,
																ADT_L1_1553_INT *int_buffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_IQ_ReadNewRawEntries(ADT_L0_UINT32 devID,
																	ADT_L0_UINT32 maxNumEntries,
																	ADT_L0_UINT32 *pNumEntries,
																	ADT_L1_1553_INT *int_buffer );
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_SetIntSeqNum(ADT_L0_UINT32 devID,
									   ADT_L0_UINT32 seqNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_INT_GetIntSeqNum(ADT_L0_UINT32 devID,
									   ADT_L0_UINT32 *pSeqNum);

/* 1553 Bus Controller */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_Init(ADT_L0_UINT32 devID,
								  ADT_L0_UINT32 max_num_msgs,
								  ADT_L0_UINT32 minors_per_major,
								  ADT_L0_UINT32 bcCsr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_Close(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_CDPAllocate(ADT_L0_UINT32 devID,
											ADT_L0_UINT32 msgnum,
											ADT_L0_UINT32 numCDP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_CDPFree(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 msgnum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_Write(ADT_L0_UINT32 devID,
									  ADT_L0_UINT32 msgnum,
									  ADT_L1_1553_BC_CB *bccb);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_Read(ADT_L0_UINT32 devID,
									 ADT_L0_UINT32 msgnum,
									 ADT_L1_1553_BC_CB *bccb);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_ReadWords(ADT_L0_UINT32 devID, ADT_L0_UINT32 msgnum, 
										ADT_L0_UINT32 wordOffset,
										ADT_L0_UINT32 numOfWords,
										ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_CDPWrite(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 msgnum,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L1_1553_CDP *pCdp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_WriteWords(ADT_L0_UINT32 devID, ADT_L0_UINT32 msgnum, 
										ADT_L0_UINT32 wordOffset,
										ADT_L0_UINT32 numOfWords,
										ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_CDPWriteWords(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 msgnum,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 wordOffset,
										 ADT_L0_UINT32 numOfWords,
										 ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_CDPRead(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 msgnum,
										ADT_L0_UINT32 cdpNum,
										ADT_L1_1553_CDP *pCdp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_CDPReadWords(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 msgnum,
										ADT_L0_UINT32 cdpNum,
										ADT_L0_UINT32 wordOffset,
										ADT_L0_UINT32 numOfWords,
										ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_Start(ADT_L0_UINT32 devID,
								   ADT_L0_UINT32 msgnum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_Stop(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_AperiodicSend(ADT_L0_UINT32 devID,
										   ADT_L0_UINT32 priority,
										   ADT_L0_UINT32 msgnum,
										   ADT_L0_UINT32 LPAMtime);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_IsRunning(ADT_L0_UINT32 devID,
									   ADT_L0_UINT32 *pIsRunning);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_AperiodicIsRunning(ADT_L0_UINT32 devID,
												ADT_L0_UINT32 priority,
												ADT_L0_UINT32 *pIsRunning);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_GetFrameCount(ADT_L0_UINT32 devID,
										   ADT_L0_UINT32 *pFrameCount);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_InjCmdWordError(ADT_L0_UINT32 devID,
											 ADT_L0_UINT32 msgNum,
											 ADT_L0_UINT32 cmd1or2,
											 ADT_L0_UINT32 syncErr,
											 ADT_L0_UINT32 manchesterErr,
											 ADT_L0_UINT32 parityErr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_ReadCmdWordError(ADT_L0_UINT32 devID,
											  ADT_L0_UINT32 msgNum,
											  ADT_L0_UINT32 cmd1or2,
											  ADT_L0_UINT32 *pSyncErr,
											  ADT_L0_UINT32 *pManchesterErr,
											  ADT_L0_UINT32 *pParityErr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_SetAddressBranchValues(ADT_L0_UINT32 devID, 
																		ADT_L0_UINT32 msgNum, 
																		ADT_L0_UINT32 srcMsgNum, 
																		ADT_L0_UINT32 srcCdpNum, 
																		ADT_L0_UINT32 srcWordOffset, 
																		ADT_L0_UINT32 maskValue, 
																		ADT_L0_UINT32 compareValue, 
																		ADT_L0_UINT32 destMsgNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_GetAddr(ADT_L0_UINT32 devID, 
										ADT_L0_UINT32 msgnum, 
										ADT_L0_UINT32 *pAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BC_CB_CDP_GetAddr(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 msgnum,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 *pAddr);

/* 1553 Remote Terminal */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_Init(ADT_L0_UINT32 devID,
								  ADT_L0_UINT32 rtAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_Close(ADT_L0_UINT32 devID,
								   ADT_L0_UINT32 rtAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_Start(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_Stop(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_Enable(ADT_L0_UINT32 devID,
								   ADT_L0_UINT32 rtAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_Disable(ADT_L0_UINT32 devID,
								  ADT_L0_UINT32 rtAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_Monitor(ADT_L0_UINT32 devID,
									 ADT_L0_UINT32 rtAddr,
									 ADT_L0_UINT32 isMonitor);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SetRespTime(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 respTime100ns);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_GetRespTime(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 * pRespTime100ns);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_InjStsWordError(ADT_L0_UINT32 devID,
											 ADT_L0_UINT32 rtAddr,
											 ADT_L0_UINT32 syncErr,
											 ADT_L0_UINT32 manchesterErr,
											 ADT_L0_UINT32 parityErr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_ReadStsWordError(ADT_L0_UINT32 devID,
											  ADT_L0_UINT32 rtAddr,
											  ADT_L0_UINT32 *pSyncErr,
											  ADT_L0_UINT32 *pManchesterErr,
											  ADT_L0_UINT32 *pParityErr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SetOptions(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 allowDBC,
										ADT_L0_UINT32 txInh_A,
										ADT_L0_UINT32 txInh_B,
										ADT_L0_UINT32 clrSRonTxVectorWd);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_GetOptions(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 *pAllowDBC,
										ADT_L0_UINT32 *pTxInh_A,
										ADT_L0_UINT32 *pTxInh_B,
										ADT_L0_UINT32 *pClrSRonTxVectorWd);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SetSingleRTAddr(ADT_L0_UINT32 devID,
											 ADT_L0_UINT32 rtAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_GetSingleRTAddr(ADT_L0_UINT32 devID,
											 ADT_L0_UINT32 *pRtAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_GetExternalRTAddr(ADT_L0_UINT32 devID,
											   ADT_L0_UINT32 *pRtAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_GetLastCmd(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 *pLastCmd);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_StatusWrite(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 stsWord);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_StatusRead(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 *pStsWord);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_LegalizationWrite(ADT_L0_UINT32 devID,
												  ADT_L0_UINT32 rtAddr,
												  ADT_L0_UINT32 tr,
												  ADT_L0_UINT32 subAddr,
												  ADT_L0_UINT32 illegalBits);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_LegalizationRead(ADT_L0_UINT32 devID,
												 ADT_L0_UINT32 rtAddr,
												 ADT_L0_UINT32 tr,
												 ADT_L0_UINT32 subAddr,
												 ADT_L0_UINT32 *pIllegalBits);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_LegalizationWrite(ADT_L0_UINT32 devID,
												  ADT_L0_UINT32 rtAddr,
												  ADT_L0_UINT32 tr,
												  ADT_L0_UINT32 modeCode,
												  ADT_L0_UINT32 illegalBits);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_LegalizationRead(ADT_L0_UINT32 devID,
												 ADT_L0_UINT32 rtAddr,
												 ADT_L0_UINT32 tr,
												 ADT_L0_UINT32 modeCode,
												 ADT_L0_UINT32 *pIllegalBits);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_CDPAllocate(ADT_L0_UINT32 devID,
											ADT_L0_UINT32 rtAddr,
											ADT_L0_UINT32 tr,
											ADT_L0_UINT32 subAddr,
											ADT_L0_UINT32 numCDP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_CDPFree(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 tr,
										ADT_L0_UINT32 subAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_CDPWrite(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 subAddr,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L1_1553_CDP *pCdp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_CDPWriteWords(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 subAddr,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 wordOffset,
										 ADT_L0_UINT32 numOfWords,
										 ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_CDPRead(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 tr,
										ADT_L0_UINT32 subAddr,
										ADT_L0_UINT32 cdpNum,
										ADT_L1_1553_CDP *pCdp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_CDPReadWords(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 subAddr,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 wordOffset,
										 ADT_L0_UINT32 numOfWords,
										 ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_CDPAllocate(ADT_L0_UINT32 devID,
											ADT_L0_UINT32 rtAddr,
											ADT_L0_UINT32 tr,
											ADT_L0_UINT32 modeCode,
											ADT_L0_UINT32 numCDP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_CDPFree(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 tr,
										ADT_L0_UINT32 modeCode);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_CDPWrite(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 modeCode,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L1_1553_CDP *pCdp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_CDPWriteWords(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 modeCode,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 wordOffset,
										 ADT_L0_UINT32 numOfWords,
										 ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_CDPRead(ADT_L0_UINT32 devID,
										ADT_L0_UINT32 rtAddr,
										ADT_L0_UINT32 tr,
										ADT_L0_UINT32 modeCode,
										ADT_L0_UINT32 cdpNum,
										ADT_L1_1553_CDP *pCdp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_CDPReadWords(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 modeCode,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 wordOffset,
										 ADT_L0_UINT32 numOfWords,
										 ADT_L0_UINT32 *pWords);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_SA_CDP_GetAddr(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 subAddr,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 *pAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_RT_MC_CDP_GetAddr(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 tr,
										 ADT_L0_UINT32 modeCode,
										 ADT_L0_UINT32 cdpNum,
										 ADT_L0_UINT32 *pAddr);

/* 1553 Bus Monitor */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_Config(ADT_L0_UINT32 devID,
									ADT_L0_UINT32 options);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_Start(ADT_L0_UINT32 dev_num);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_Stop(ADT_L0_UINT32 dev_num);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_Clear(ADT_L0_UINT32 dev_num);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_FilterRead(ADT_L0_UINT32 devID, ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 *pRxFilters, ADT_L0_UINT32 *pTxFilters);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_FilterWrite(ADT_L0_UINT32 devID, ADT_L0_UINT32 rtAddr,
										 ADT_L0_UINT32 rxFilters, ADT_L0_UINT32 txFilters);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_BufferCreate(ADT_L0_UINT32 devID, ADT_L0_UINT32 numMsgs);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_BufferFree(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_ReadNewMsgs(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 maxNumMsgs,
										 ADT_L0_UINT32 *pNumMsgs,
										 ADT_L1_1553_CDP *pMsgBuffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_ReadNewMsgsDMA(ADT_L0_UINT32 devID,
										 ADT_L0_UINT32 maxNumMsgs,
										 ADT_L0_UINT32 *pNumMsgs,
										 ADT_L1_1553_CDP *pMsgBuffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_CDPWrite(ADT_L0_UINT32 devID,
									  ADT_L0_UINT32 cdpNum,
									  ADT_L1_1553_CDP *pCdp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_BM_CDPRead(ADT_L0_UINT32 devID,
									 ADT_L0_UINT32 cdpNum,
									 ADT_L1_1553_CDP *pCdp);

/* 1553 Playback */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_SetRtResponse(ADT_L0_UINT32 devID,
										   ADT_L0_UINT32 rtResp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_GetRtResponse(ADT_L0_UINT32 devID,
										   ADT_L0_UINT32 *pRtResp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_Allocate(ADT_L0_UINT32 devID,
									  ADT_L0_UINT32 numPkts);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_Free(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_CDPWrite(ADT_L0_UINT32 devID,
									  ADT_L1_1553_CDP *pCdp,
									  ADT_L0_UINT32 options,
									  ADT_L0_UINT32 isFirstMsg);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_Start(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_Stop(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_PB_IsRunning(ADT_L0_UINT32 devID,
									   ADT_L0_UINT32 *pIsRunning);

/* 1553 Signal Generator */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_Configure(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_CreateSGCB(ADT_L0_UINT32 devID,
										char bus,
										ADT_L0_UINT32 timeHigh,
										ADT_L0_UINT32 timeLow,
										ADT_L0_UINT32 *pVectors,
										ADT_L0_UINT32 numVectors);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_Free(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_Start(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_Stop(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_IsRunning(ADT_L0_UINT32 devID,
									   ADT_L0_UINT32 *pIsRunning);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_WordToVectors(ADT_L0_UINT32 m1553word,
										ADT_L0_UINT32 *pVectors,
										ADT_L0_UINT32 sizeInWords,
										ADT_L0_UINT32 *pNumVectors);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_1553_SG_AddVectors(ADT_L0_UINT32 numVec,
										ADT_L0_UINT32 vector2bit,
										ADT_L0_UINT32 *pVectors,
										ADT_L0_UINT32 sizeInWords,
										ADT_L0_UINT32 *pNumVectors);


/********** A429 Functions **********/
/* A429 General */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_InitDefault(ADT_L0_UINT32 devID,
													   ADT_L0_UINT32 numIQEntries);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_InitDefault_ExtendedOptions(ADT_L0_UINT32 devID,
																	   ADT_L0_UINT32 numIQEntries,
																	   ADT_L0_UINT32 startupOptions);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_InitDevice(ADT_L0_UINT32 devID,
													  ADT_L0_UINT32 numIQEntries);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_GetConfig(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 *pChanConfig);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_GetPEInfo(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 *peInfo);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TimeSet(ADT_L0_UINT32 devID,
												   ADT_L0_UINT32 timeHigh,
												   ADT_L0_UINT32 timeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TimeGet(ADT_L0_UINT32 devID,
												   ADT_L0_UINT32 *pTimeHigh,
												   ADT_L0_UINT32 *pTimeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_PBTimeSet(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 timeHigh,
													 ADT_L0_UINT32 timeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_PBTimeGet(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 *pTimeHigh,
													 ADT_L0_UINT32 *pTimeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TimeClear(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_IrigLatchedTimeGet(ADT_L0_UINT32 devID, 
															  ADT_L0_UINT32 *pIrigTimeHigh, ADT_L0_UINT32 *pIrigTimeLow, 
															  ADT_L0_UINT32 *pIntTimeHigh, ADT_L0_UINT32 *pIntTimeLow, 
															  ADT_L0_UINT32 *pDeltaTimeHigh, ADT_L0_UINT32 *pDeltaTimeLow);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_UseExtClk(ADT_L0_UINT32 devID,
													 ADT_L0_UINT32 useExtClk,
													 ADT_L0_UINT32 clkFreq);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SC_ArmTrigger(ADT_L0_UINT32 devID,
														 ADT_L0_UINT32 rxChan);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SC_ReadBuffer(ADT_L0_UINT32 devID,
														 ADT_L0_UINT32 rxChan,
														 ADT_L0_UINT8 *buffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_IntervalTimerGet(ADT_L0_UINT32 devID, 
															ADT_L0_UINT32 *pIntvlTmrReg);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_IntervalTimerSet(ADT_L0_UINT32 devID, 
															ADT_L0_UINT32 intvlTmrReg);

/* A429 Interrupt */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_EnableInt(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_DisableInt(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_CheckDeviceIntPending(ADT_L0_UINT32 devID,
																	  ADT_L0_UINT32 *pIsIntPending);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_IQ_ReadEntry(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 *pType,
															ADT_L0_UINT32 *pInfo);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_IQ_ReadNewEntries(ADT_L0_UINT32 devID,
																 ADT_L0_UINT32 maxNumEntries,
																 ADT_L0_UINT32 *pNumEntries,
																 ADT_L0_UINT32 *pType,
																 ADT_L0_UINT32 *pInfo);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_IQ_ReadRawEntry( ADT_L0_UINT32 devID,
																ADT_L1_A429_INT *int_buffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_IQ_ReadNewRawEntries(ADT_L0_UINT32 devID,
																	ADT_L0_UINT32 maxNumEntries,
																    ADT_L0_UINT32 *pNumEntries,
																	ADT_L1_A429_INT *int_buffer );
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_SetIntSeqNum(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 seqNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_INT_GetIntSeqNum(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 *pSeqNum);

/* A429 Transmit */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_Init(ADT_L0_UINT32 devID,
														   ADT_L0_UINT32 TxChanNum,
														   ADT_L0_UINT32 BitRateHz,
														   ADT_L0_UINT32 numTXCB);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_Close(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 TxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_TXPAllocate(ADT_L0_UINT32 devID,
																	 ADT_L0_UINT32 TxChanNum,
																	 ADT_L0_UINT32 msgnum,
																	 ADT_L0_UINT32 numTXP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_TXPFree(ADT_L0_UINT32 devID,
																 ADT_L0_UINT32 TxChanNum,
																 ADT_L0_UINT32 msgnum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_Write(ADT_L0_UINT32 devID,
															   ADT_L0_UINT32 TxChanNum,
															   ADT_L0_UINT32 msgnum,
															   ADT_L1_A429_TXCB *txcb);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_Read(ADT_L0_UINT32 devID,
															  ADT_L0_UINT32 TxChanNum,
															  ADT_L0_UINT32 msgnum,
															  ADT_L1_A429_TXCB *txcb);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_TXPWrite(ADT_L0_UINT32 devID,
																  ADT_L0_UINT32 TxChanNum,
																  ADT_L0_UINT32 msgnum,
																  ADT_L0_UINT32 txpNum,
																  ADT_L1_A429_TXP *pTxp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_TXPRead(ADT_L0_UINT32 devID,
																 ADT_L0_UINT32 TxChanNum,
																 ADT_L0_UINT32 msgnum,
																 ADT_L0_UINT32 txpNum,
																 ADT_L1_A429_TXP *pTxp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_Start(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 TxChanNum,
															ADT_L0_UINT32 msgnum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_Stop(ADT_L0_UINT32 devID,
														   ADT_L0_UINT32 TxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_IsRunning(ADT_L0_UINT32 devID,
																ADT_L0_UINT32 TxChanNum,
																ADT_L0_UINT32 *pIsRunning);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_SendLabel(ADT_L0_UINT32 devID,
																ADT_L0_UINT32 TxChanNum,
																ADT_L0_UINT32 Label);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_SendLabelBlock(ADT_L0_UINT32 devID, 
																	 ADT_L0_UINT32 TxChanNum, 
																	 ADT_L0_UINT32 numLabels, 
																	 ADT_L0_UINT32 *pLabels);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_SetConfig(ADT_L0_UINT32 devID,
																ADT_L0_UINT32 TxChanNum,
																ADT_L0_UINT32 CSR1,
																ADT_L0_UINT32 CSR2);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_GetConfig(ADT_L0_UINT32 devID,
																ADT_L0_UINT32 TxChanNum,
																ADT_L0_UINT32 *pCSR1,
																ADT_L0_UINT32 *pCSR2);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_GetTxpCount(ADT_L0_UINT32 devID,
																  ADT_L0_UINT32 TxChanNum,
																  ADT_L0_UINT32 *txpCnt);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_AperiodicSend(ADT_L0_UINT32 devID, 
																	ADT_L0_UINT32 TxChanNum, 
																	ADT_L0_UINT32 msgnum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_AperiodicIsRunning(ADT_L0_UINT32 devID, 
																		 ADT_L0_UINT32 TxChanNum, 
																		 ADT_L0_UINT32 *pIsRunning);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_GetAddr(ADT_L0_UINT32 devID, 
																 ADT_L0_UINT32 TxChanNum, 
																 ADT_L0_UINT32 msgnum, 
																 ADT_L0_UINT32 *pAddr);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_CB_TXP_GetAddr(ADT_L0_UINT32 devID, 
																	 ADT_L0_UINT32 TxChanNum, 
																	 ADT_L0_UINT32 msgnum, 
																	 ADT_L0_UINT32 txpNum,
																	 ADT_L0_UINT32 *pAddr);


/* A429 Receive */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_Init(ADT_L0_UINT32 devID,
														   ADT_L0_UINT32 RxChanNum,
														   ADT_L0_UINT32 BitRateHz,
														   ADT_L0_UINT32 numRxP,
														   ADT_L0_UINT32 options);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_Close(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 RxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_Start(ADT_L0_UINT32 devID,
															ADT_L0_UINT32 RxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_Stop(ADT_L0_UINT32 devID,
														   ADT_L0_UINT32 RxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_ReadNewRxPs(ADT_L0_UINT32 devID,
																  ADT_L0_UINT32 RxChanNum,
																  ADT_L0_UINT32 maxNumRxPs,
																  ADT_L0_UINT32 *pNumRxPs,
																  ADT_L1_A429_RXP *pRxPBuffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_ReadNewRxPsDMA(ADT_L0_UINT32 devID,
																  ADT_L0_UINT32 RxChanNum,
																  ADT_L0_UINT32 maxNumRxPs,
																  ADT_L0_UINT32 *pNumRxPs,
																  ADT_L1_A429_RXP *pRxPBuffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_ReadRxP(ADT_L0_UINT32 devID,
															  ADT_L0_UINT32 RxChanNum,
															  ADT_L0_UINT32 RxP_index,
															  ADT_L1_A429_RXP *pRxP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_CVTReadRxP(ADT_L0_UINT32 devID,
																  ADT_L0_UINT32 RxChanNum,
																  ADT_L0_UINT32 labelIndex,
																  ADT_L1_A429_RXP *pRxP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_WriteRxP(ADT_L0_UINT32 devID,
															   ADT_L0_UINT32 RxChanNum,
															   ADT_L0_UINT32 RxP_index,
															   ADT_L1_A429_RXP *pRxP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_CVTWriteRxP(ADT_L0_UINT32 devID,
																  ADT_L0_UINT32 RxChanNum,
																  ADT_L0_UINT32 labelIndex,
																  ADT_L1_A429_RXP *pRxP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_SetConfig(ADT_L0_UINT32 devID,
																ADT_L0_UINT32 RxChanNum,
																ADT_L0_UINT32 Setup1,
																ADT_L0_UINT32 Setup2);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_GetConfig(ADT_L0_UINT32 devID,
																ADT_L0_UINT32 RxChanNum,
																ADT_L0_UINT32 *pSetup1,
																ADT_L0_UINT32 *pSetup2);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_SetMaskCompare(ADT_L0_UINT32 devID,
																	 ADT_L0_UINT32 RxChanNum,
																	 ADT_L0_UINT32 mask1,
																	 ADT_L0_UINT32 compare1,
																	 ADT_L0_UINT32 mask2,
																	 ADT_L0_UINT32 compare2);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RX_Channel_GetMaskCompare(ADT_L0_UINT32 devID,
																	 ADT_L0_UINT32
																	 RxChanNum,
																	 ADT_L0_UINT32 *pMask1,
																	 ADT_L0_UINT32 *pCompare1,
																	 ADT_L0_UINT32 *pMask2,
																	 ADT_L0_UINT32 *pCompare2);

ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A717_RX_Channel_SetConfig(ADT_L0_UINT32 devID,
																	 ADT_L0_UINT32 RxChanNum,
																	 ADT_L0_UINT32 Csr,
																	 ADT_L0_UINT32 Sync1,
																	 ADT_L0_UINT32 Sync2,
																	 ADT_L0_UINT32 Sync3,
																	 ADT_L0_UINT32 Sync4);

ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A717_RX_Channel_GetConfig(ADT_L0_UINT32 devID,
																	 ADT_L0_UINT32  RxChanNum,
																	 ADT_L0_UINT32 *Csr,
																	 ADT_L0_UINT32 *pSync1,
																	 ADT_L0_UINT32 *pSync2,
																	 ADT_L0_UINT32 *pSync3,
																	 ADT_L0_UINT32 *pSync4);

/* A429 Multi-Channel Receive */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RXMC_BufferCreate(ADT_L0_UINT32 devID,
															 ADT_L0_UINT32 numRxP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RXMC_BufferFree(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RXMC_ReadNewRxPs(ADT_L0_UINT32 devID,
														   ADT_L0_UINT32 maxNumRxPs,
														   ADT_L0_UINT32 *pNumRxPs,
														   ADT_L1_A429_RXP *pRxPBuffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RXMC_ReadNewRxPsDMA(ADT_L0_UINT32 devID,
														   ADT_L0_UINT32 maxNumRxPs,
														   ADT_L0_UINT32 *pNumRxPs,
														   ADT_L1_A429_RXP *pRxPBuffer);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RXMC_ReadRxP(ADT_L0_UINT32 devID,
														ADT_L0_UINT32 RxP_index,
														ADT_L1_A429_RXP *pRxP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_RXMC_WriteRxP(ADT_L0_UINT32 devID,
														ADT_L0_UINT32 RxP_index,
														ADT_L1_A429_RXP *pRxP);

/* A429 Playback */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_Init(ADT_L0_UINT32 devID,
															  ADT_L0_UINT32 TxChanNum,
															  ADT_L0_UINT32 BitRateHz,
															  ADT_L0_UINT32 numTXCB);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_Close(ADT_L0_UINT32 devID,
															   ADT_L0_UINT32 TxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_CB_PXPAllocate(ADT_L0_UINT32 devID,
																		ADT_L0_UINT32 TxChanNum,
																		ADT_L0_UINT32 PBCBnum,
																		ADT_L0_UINT32 numPXP);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_CB_PXPFree(ADT_L0_UINT32 devID,
																	ADT_L0_UINT32 TxChanNum,
																	ADT_L0_UINT32 PBCBnum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_CB_Write(ADT_L0_UINT32 devID,
																 ADT_L0_UINT32 TxChanNum,
																 ADT_L0_UINT32 PBCBnum,
																 ADT_L1_A429_TXCB *txcb);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_CB_Read(ADT_L0_UINT32 devID,
																 ADT_L0_UINT32 TxChanNum,
																 ADT_L0_UINT32 PBCBnum,
																 ADT_L1_A429_TXCB *txcb);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_CB_PXPRead(ADT_L0_UINT32 devID,
																	ADT_L0_UINT32 TxChanNum,
																	ADT_L0_UINT32 PBCBnum,
																	ADT_L0_UINT32 txpNum,
																	ADT_L1_A429_RXP *pTxp);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_Start(ADT_L0_UINT32 devID,
															   ADT_L0_UINT32 TxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_Stop(ADT_L0_UINT32 devID,
															  ADT_L0_UINT32 TxChanNum);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_PB_Start(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_PB_Stop(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_IsRunning(ADT_L0_UINT32 devID,
																   ADT_L0_UINT32 TxChanNum,
																   ADT_L0_UINT32 *pIsRunning);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_SetConfig(ADT_L0_UINT32 devID,
																   ADT_L0_UINT32 TxChanNum,
																   ADT_L0_UINT32 CSR1,
																   ADT_L0_UINT32 CSR2);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_GetConfig(ADT_L0_UINT32 devID,
																   ADT_L0_UINT32 TxChanNum,
																   ADT_L0_UINT32 *pCSR1,
																   ADT_L0_UINT32 *pCSR2);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_TX_Channel_PB_RXPWrite(ADT_L0_UINT32 devID,
																  ADT_L0_UINT32 txChanNum,
																  ADT_L0_UINT32 numRxps,
																  ADT_L1_A429_RXP *RxpBuffer,
																  ADT_L0_UINT32 options,
																  ADT_L0_UINT32 isFirstMsg);

/* A429 Signal Generator */
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_Configure(ADT_L0_UINT32 devID,
														ADT_L0_UINT32 txChannel,
														ADT_L0_UINT32 slewRate);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_CreateSGCB(ADT_L0_UINT32 devID,
														 ADT_L0_UINT32 timeHigh,
														 ADT_L0_UINT32 timeLow,
														 ADT_L0_UINT32 *pVectors,
														 ADT_L0_UINT32 numVectors);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_Free(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_Start(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_Stop(ADT_L0_UINT32 devID);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_IsRunning(ADT_L0_UINT32 devID,
														ADT_L0_UINT32 *pIsRunning);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_WordToVectors(ADT_L0_UINT32 a429word,
															ADT_L0_UINT32 halfBitTime100ns,
															ADT_L0_UINT32 *pVectors,
															ADT_L0_UINT32 sizeInWords,
															ADT_L0_UINT32 *pNumVectors);
ADT_L0_UINT32 ADT_L0_CALL_CONV ADT_L1_A429_SG_AddVectors(ADT_L0_UINT32 numVec,
														 ADT_L0_UINT32 vector2bit,
														 ADT_L0_UINT32 *pVectors,
														 ADT_L0_UINT32 sizeInWords,
														 ADT_L0_UINT32 *pNumVectors);


#ifdef __cplusplus
}
#endif

#endif

